Zobrazeno 1 - 10
of 61
pro vyhledávání: '"B. Tavel"'
Autor:
David Barge, Philippe Garnier, Tony Vessa, B. Tavel, Didier Lévy, Anne Sophie Larrea, Y. Gomez, B. Pernet, A. Torres, C. Henderson
Publikováno v:
ECS Transactions. 11:257-264
Pre gate oxide and especially "Double Gate Oxide" cleans are the most critical surface preparation steps in the semiconductor industry. This paper describes the key parameters to perform this kind of operations on a fully integrated single wafer clea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34d999bd58338acdc8c4302873c1303e
https://doi.org/10.1149/1.2779387
https://doi.org/10.1149/1.2779387
Autor:
L. Vishnubhotla, Pierre Morin, Robert Fox, S. Boret, R. Difrenza, B. Tavel, K. Rochereau, P. Stolk, C. Detcheverry, Daniel Gloria, M.T. Basso, M. Woo, M. Broekaart, B. Duriez, P. Garnier, D. Reber, Y. Trouille, J. Bienacel, M. Denais, D. Barge, C. Ortolland, K. Cooper, Frederic Boeuf, S. Vanbergue, Vincent Huard, Jean-Damien Chapon, J. Belledent, Pascal Gouraud, Nicolas Planes, Franck Arnaud, P. Abramowitz, E. Saboure, Y. Laplanche, C. Julien, M. Bidaud, M. Marin, Romain Gwoziecki
Publikováno v:
Solid-State Electronics. 50:573-578
A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2a1f438c93e06660abf827ae1f1027bf
https://doi.org/10.1016/j.sse.2006.03.030
https://doi.org/10.1016/j.sse.2006.03.030
Autor:
Francois Leverd, Christophe Regnier, J. Bustos, B. Tavel, Thomas Skotnicki, Francois Wacquant, S. Harrison, Philippe Coronel, A. Beverina
Publikováno v:
Microelectronic Engineering. 72:321-325
We report on a new concept for realization of transistors with high-k oxide by deposition through the contact holes. This new integration allows low thermal budget for the high-k film (deposited after source and drain anneal), no particular contamina
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b35cd6ee77a21820fda615da8e09934
https://doi.org/10.1016/j.mee.2004.01.030
https://doi.org/10.1016/j.mee.2004.01.030
Autor:
K. Rochereau, P. Stolk, S. Jullian, David Roy, Alessandro Dezzani, B. Duriez, T. Devoivre, Franck Arnaud, R. Boulestin, B. Tavel, R. Difrenza
Publikováno v:
Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005..
The 65 nm process has been optimized through thermal budget and implant of halo and LDD to reduce gate impact. It provides the best matching results ever reported to our knowledge, i.e. A/sub Vt/ of 2.1 and 1.9 mV./spl mu/m for NMOS and PMOS respecti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4ea2ce61b969744cc12c459dd6042ce
https://doi.org/10.1109/icmts.2005.1452247
https://doi.org/10.1109/icmts.2005.1452247
Autor:
N. Bicais-Lepinay, V. DeJonghe, B. Tavel, M. Jurdit, Stephane Denorme, C. Boccaccio, F. Andre, M. Aminpur, S. Manakli, M. Broekaart, J. Todeschini, C. Laviron, S. Smith, B. Icard, C. Reddy, B. Borot, Nicolas Planes, S. Jullian, Thomas Skotnicki, F. Guyader, Frederic Boeuf, J.P. Jacquemin, P. Morini, J. Bustos, N. Gierczynski, Pascal Gouraud, P. Brun, Franck Arnaud, M. Mellier, F. Salvetti, C. Ortolland, B. Duriez, Laurent Pain
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
This work highlights the realization and 0.248/spl mu/m/sup 2/ to 0.334/spl mu/m/sup 2/ SRAM bit-cells with conventional bulk technology based on 19/spl Aring/ CET SiON gate oxide, poly-silicon gate electrode, and mobility enhancement techniques for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd5d5402c851ccecf8dcda10c729bbfe
https://doi.org/10.1109/.2005.1469240
https://doi.org/10.1109/.2005.1469240
Autor:
Frédéric Martinez, Frederic Boeuf, J. C. Vildeuil, G. Neau, Thomas Skotnicki, M. Bidaud, B. Tavel, Emmanuel Vincent, C. Leyris, Alain Hoffmann, M. Valenza, D. Barge
Publikováno v:
Microelectronic Engineering
Microelectronic Engineering, 2005, vol 80, pp 54-57. ⟨10.1016/j.mee.2005.04.043⟩
Microelectronic Engineering, Elsevier, 2005, vol 80, pp 54-57. ⟨10.1016/j.mee.2005.04.043⟩
Microelectronic Engineering, 2005, vol 80, pp 54-57. ⟨10.1016/j.mee.2005.04.043⟩
Microelectronic Engineering, Elsevier, 2005, vol 80, pp 54-57. ⟨10.1016/j.mee.2005.04.043⟩
International audience; A characterization of traps in ultrathin-oxide MOSFETs by low frequency noise measurements is presented. Drain and gate current noise measurements are investigated. 1/f drain noise magnitude allows extraction of slow oxide int
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8d3929c4879cce5c32d6a4bdaef15faf
https://hal.science/hal-00327712
https://hal.science/hal-00327712
Autor:
F. Arnaud, M. Bidaud, G. Ribes, Vincent Huard, Chittoor Parthasarathy, Alain Bravaix, F. Perrier, P. Stolk, L. Vishnubhotla, M. Denais, David Barge, B. Tavel, Nathalie Revil, Y. Rey-Tauriac
Publikováno v:
IEEE International Integrated Reliability Workshop Final Report, 2004.
We have developed in this work a new characterization methodology which includes stressing and measurement in a single experimental step. This overcomes the influence of the hole detrapping effect in ultra-thin gate-oxides (T/sub OX/=1.4-1.6 nm) and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1c1d2cd245379949963fb451823b594
https://doi.org/10.1109/irws.2004.1422753
https://doi.org/10.1109/irws.2004.1422753
Autor:
R. Difrenza, P. Stolk, M. Bidaud, Pierre Morin, M. Woo, B. Tavel, R. Wacquant, M. Denais, Franck Arnaud, R. Boeuf, F. Payet, D. Reber, N. Cagnat, K. Rochereau, M. Marin, M.T. Basso, B. Duriez, C. Ortolland, Damien Lenoble, Y. Laplanche, C. Dachs, H. Brut, David Roy, R. Palla, D. Barge
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
This paper demonstrates a full gate stack optimization by using post gate anneal (PGA) solution coupled with both germanium and fluorine gate predoping. We obtained a large carrier mobility enhancement for both NMOS (+50%) and PMOS (+20%) thanks to a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd2c977b7d9f1b89f67ddec77baf9fe2
https://doi.org/10.1109/iedm.2004.1419311
https://doi.org/10.1109/iedm.2004.1419311
Autor:
J. Todeschini, M. Bidaud, J. Rosa, H. Bernard, Franck Arnaud, M. Jurdit, D. Sotta, B. Duriez, J. Grant, Laurent Pain, Thomas Skotnicki, N. Bicais-Lepinay, Pierre Morin, J. Bustos, C. Chaton, Francois Wacquant, R. El-Farhane, Frederic Boeuf, Pascal Gouraud, M.T. Basso, S. Manakli, S. Jullian, V. DeJonghe, B. Tavel, M. Gaillardin
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b0c59f4f0efd04c243db59f149ec997
https://doi.org/10.1109/iedm.2004.1419177
https://doi.org/10.1109/iedm.2004.1419177
Publikováno v:
AIP Conference Proceedings.
This contribution addresses several important topics about 1/f noise in MOSFETs for the 65 nm node. We show that a plasma nitridation technique can significantly improve the 1/f noise performances of the device providing that the insulator is thick e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b351d240252f4a3ee346a5fb08a8ff3
https://doi.org/10.1063/1.2036730
https://doi.org/10.1063/1.2036730