Zobrazeno 1 - 10
of 146
pro vyhledávání: '"B. Rouzeyre"'
Publikováno v:
2022 IEEE European Test Symposium (ETS).
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Publikováno v:
HLDVT'03: High Level Design Validation and Test Workshop
HLDVT'03: High Level Design Validation and Test Workshop, San Francisco (USA), France. pp. 129-135
HLDVT
HLDVT'03: High Level Design Validation and Test Workshop, San Francisco, United States. pp.129-135
HLDVT'03: High Level Design Validation and Test Workshop, San Francisco (USA), France. pp. 129-135
HLDVT
HLDVT'03: High Level Design Validation and Test Workshop, San Francisco, United States. pp.129-135
Full sequential equivalence checking by state space traversal has been shown to be unpractical for large designs. To address state space explosion new approaches have been proposed that exploit structural characteristics of a design and make use of m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fa6cca32651267b939fcdd083796fe3a
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269707
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269707
Publikováno v:
2007 Ph.D Research in Microelectronics and Electronics Conference.
During the production phase of microelectronics systems, one of the fundamental steps is to check if the system works fine. This step is called the test of integrated circuits. Furthermore, cost reduction of these tests has become a major axe of rese
Publikováno v:
9th IEEE European Test Symposium
ETS: European Test Symposium
ETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. pp.80-85, ⟨10.1109/ETSYM.2004.1347611⟩
European Test Symposium
ETS: European Test Symposium
ETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. pp.80-85, ⟨10.1109/ETSYM.2004.1347611⟩
European Test Symposium
This paper discusses the extensions to the automatic SOC test architecture optimization tool TR-ARCHITECT that allow the user to partially specify the resulting test architecture. We describe a novel Test Architecture Specification (TAS) language, in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::95e379a3a21b585f5c182e1b736adc90
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00108903
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00108903
Publikováno v:
Proceedings of the European Conference on Design Automation..
Presents a new partitioning method for finite state machines (FSMs). The method is particularly well suited for mu -controller circuits. It consists in grouping the mu -instructions of the control graph into classes according to a compatibility prope
Publikováno v:
Proceedings Design, Automation and Test in Europe.
Publikováno v:
Proceedings European Design and Test Conference. ED & TC 97.
Publikováno v:
Proceedings the European Design and Test Conference. ED&TC 1995.
Publikováno v:
HLDVT
A new, compact, canonical representation for arithmetic expressions, called Taylor expansion diagram, is presented. This representation is based on a non-binary decomposition principle. It treats the expression as a continuous, differentiable functio