Zobrazeno 1 - 10
of 28
pro vyhledávání: '"B. Neurauter"'
Akademický článek
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Autor:
Christian Wicpalek, T. Mayer, Stefan Tertinek, Peter Preyler, Robert Weigel, Thomas Ussmueller, T. Buckel, B. Neurauter
Publikováno v:
2014 44th European Microwave Conference.
Akademický článek
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Autor:
Y. Liu, T. Mayer, Z. Boos, V. Neubauer, Y. Chen, B. Neurauter, U. Vollerbruch, C. Wicpalek, L. Maurert
Publikováno v:
2007 IEEE Asian Solid-State Circuits Conference.
A 9 GHz fully digitally controlled oscillator implemented in 65 nm CMOS technology is presented. This is the first DCO implemented at 9 GHz which covers all transmitter (TX) and receiver (RX) bands of GSM/EDGE and UMTS except Band VII. It covers a co
Publikováno v:
RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE Radio Frequency integrated Circuits.
A GPRS RF solution using sigma-delta modulation and an EDGE RF solution using digital polar modulation are presented. The single-chip, quad-band transceivers have been implemented in a 0.13 /spl mu/m CMOS technology. The lock-in time of the sigma-del
Publikováno v:
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.
A 120 nm CMOS quad-band transceiver for GSM EDGE with a dual mode transmitter architecture and a constant gain direct conversion receiver has been developed. In GMSK mode, a direct conversion transmitter with third order /spl Sigma//spl Delta/-modula
A quad-band low power single chip direct conversion CMOS transceiver with ΣΔ-modulation loop for GSM
Autor:
J. Rubach, B. Neurauter, B. Memmler, G. Marzinger, C. Munker, E. Gotz, D. Romer, M. Simon, U. Steinacker, H. Krobel, C. Stoger, Markus Scholz, W. Schelmbauer
Publikováno v:
ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).
This paper presents a fully integrated quad band GSM transceiver with a new sigma-delta modulator architecture designed in a standard 120 nm CMOS technology. The fully integrated VCO operates at 4 GHz with a frequency range that can be programmed by
Publikováno v:
2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).
This paper presents a fractional-N modulator architecture that uses the technique of two-point-modulation. This technique allows direct modulation of the VCO within the closed loop of a high resolution PLL based fractional-N frequency synthesizer, wi
Publikováno v:
2001 IEEE MTT-S International Microwave Sympsoium Digest (Cat. No.01CH37157).
This paper presents a programmable phase-locked-loop (PLL)-based fractional-N frequency synthesizer that uses a third-order /spl Delta//spl Sigma/-modulator. The in-band phase noise of -97 dBc/Hz in the integer-mode and -94 dBc/Hz in the fractional-m
Publikováno v:
30th European Microwave Conference, 2000.
This paper presents a fractional-n frequency synthesizer that uses AC-modulation to obtain the desired fractional division value. After a brief presentation of the synthesizers' key elements a detailed noise analysis follows. Measurements from the pr