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Publikováno v:
VLSI Design
In this paper, we propose a new Variable Testability Measure (VTM) applied at the high-level synthesis stage of the circuit- design process. The proposed approach is based on Binary Decision Diagrams representing fully fhnctional blocks of a circuit,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81a1cdcc147648420249f5f147c591de
https://doi.org/10.1109/icvd.1992.658054
https://doi.org/10.1109/icvd.1992.658054
