Zobrazeno 1 - 10
of 43
pro vyhledávání: '"B. K. Madhavi"'
Publikováno v:
Handbook of Intelligent Computing and Optimization for Sustainable Development. :287-304
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3dcfd9c12ed9edc55cada5918ad8f681
https://doi.org/10.1002/9781119792642.ch14
https://doi.org/10.1002/9781119792642.ch14
Publikováno v:
International Journal of Scientific Research in Science and Technology. :35-42
In recent years, Software Defined Networking (SDN) has enabled total control over the network's data flow. SDN acts as a centralised point of administration for data and traffic management. Due to the fact that SDN is an open source software, it is m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c44132a3a3f9ca13b91833e28a180e68
https://doi.org/10.32628/ijsrst22913
https://doi.org/10.32628/ijsrst22913
In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in W
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::39220b4297fcd79fab798ef70a3f88ef
https://zenodo.org/record/4624489
https://zenodo.org/record/4624489
Publikováno v:
Circuits and Systems. :87-99
Decimal multipliers play an important role in our day to day life for commercial, financial and tax applications. Every processor multiplier acts as the basic building block which decides the performance of processor. Time and again research is going
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::946a0f0849bbdaea684b57ee2e295bc6
https://doi.org/10.4236/cs.2018.96009
https://doi.org/10.4236/cs.2018.96009
Publikováno v:
Analog Integrated Circuits and Signal Processing. 93:41-47
This paper presents the design of low noise amplifier and mixer (LIXER) circuit for wireless receiver front ends using 65 nm CMOS technology. The circuit is implemented with CMOS transistors and uses 65 nm CMOS process. Proposed LIXER circuit achieve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71e0a03c9775b7dfbbffbbcfc3f079c2
https://doi.org/10.1007/s10470-017-1034-z
https://doi.org/10.1007/s10470-017-1034-z
The main objective of this chapter is to provide high-performance, low-power solutions for VLSI system designers. As technology scales down to 32nm and below, the present CMOS technology has to face the scaling limit, such as the increased leakage po
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9826f9b4eb9f1af1f98e09cad2e92fde
https://doi.org/10.4018/978-1-7998-1393-4.ch006
https://doi.org/10.4018/978-1-7998-1393-4.ch006
Publikováno v:
Learning and Analytics in Intelligent Systems ISBN: 9783030243173
The leakage power dissipation is turning into one of the most strenuous concerns in low power VLSI circuit designs particularly with on-chip devices as it increases for every two years. The scaling down of threshold voltage has volunteered massively
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49d1a9f98aa48db257e054a54807fa80
https://doi.org/10.1007/978-3-030-24318-0_30
https://doi.org/10.1007/978-3-030-24318-0_30
Publikováno v:
2019 International Conference on Communication and Electronics Systems (ICCES).
Compressor logics are used to speed up the processing time. These structures are used for addition of Partial Products in multipliers. It reduces the complexity by reducing number of stages in addition. This paper speaks about addition of partial pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43030b982c723ba90a842429ba49d6e9
https://doi.org/10.1109/icces45898.2019.9002202
https://doi.org/10.1109/icces45898.2019.9002202
Publikováno v:
2019 6th International Conference on Signal Processing and Integrated Networks (SPIN).
This manuscript presents a novel Sample and Hold circuit with improve linearity. Designing of a clock booster is an important attribute in the proposed bootstrap circuit. This Sample and Hold circuit is designed in the 45nm CMOS process which operate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df2795eba9c9b16593f1b3eef1a3a377
https://doi.org/10.1109/spin.2019.8711660
https://doi.org/10.1109/spin.2019.8711660
Publikováno v:
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India).
Artificial intelligence an integral part of a neural network is based on mathematical equations and artificial neurons. The focus here is to implement 3 bit pattern recognition using CNTFET model in 32nm technology. Its analysis with bulk CMOS techno
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d503d2e310d853cf20e40c0816ad7efa
https://doi.org/10.1109/mos-ak.2019.8902429
https://doi.org/10.1109/mos-ak.2019.8902429