Zobrazeno 1 - 5
of 5
pro vyhledávání: '"B. J. Nathanson"'
Autor:
Subhrajit Bhattacharya, B. Gopalsamy, M. Wazlowski, Martin Ohmacht, B. J. Nathanson, Reinaldo A. Bergamaschi, D. J. Krolak, J. A. Marcella, Dirk Hoenicke, A. Gara, Valentina Salapura, Mark E. Giampapa, R. A. Haring
Publikováno v:
IBM Journal of Research and Development. 49:255-264
The Blue Gene®/L compute chip is a dual-processor system-on-a-chip capable of delivering an arithmetic peak performance of 5.6 gigaflops. To match the memory speed to the high compute performance, the system implements an aggressive three-level on-c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9599edd71b0a8a63fa0e89408c2d21ae
https://doi.org/10.1147/rd.492.0255
https://doi.org/10.1147/rd.492.0255
Autor:
Ralph Bellofatto, Dirk Hoenicke, R. A. Haring, Robert B. Tremaine, Martin Ohmacht, B. J. Nathanson, A. R. Umamaheshwaran, Dong Chen, Burkhard Steinmacher-Burow, Mark E. Giampapa, Pavlos M. Vranas, P. Heidelberger, M. Tsao, M. B. Dombrowa, Matthias A. Blumrich, Michael Wazlowski, R. Sharrar, N. R. Adiga, D.K. Beece, Suryabhan Singh, A. Gara
Publikováno v:
IBM Journal of Research and Development. 49:303-318
The Blue Gene®/L compute chip contains two PowerPC® 440 processor cores, private L2 prefetch caches, a shared L3 cache and double-data-rate synchronous dynamic random access memory (DDR SDRAM) memory controller, a collective network interface, a to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::715279d85e899e4cc797cb3a942c3474
https://doi.org/10.1147/rd.492.0303
https://doi.org/10.1147/rd.492.0303
Autor:
R. F. Stucke, B. J. Nathanson, B. Aball, M. G. Atkins, Donald G. Grice, M. Tsao, Richard A. Swetz, Douglas J. Joseph, Peter H. Hochschild, Dennis G. Shea, Craig B. Stunkel, Carl A. Bender, P. R. Varker
Publikováno v:
IBM Systems Journal. 34:185-204
The heart of an IBM SP2™ system is the HighPerformance Switch, which is a low-latency, highbandwidth switching network that binds together RISC System/6000® processors. The switch incorporates a unique combination of topology and architectural fea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::437cd40eb330e8d08ddc34fcddd46bfc
https://doi.org/10.1147/sj.342.0185
https://doi.org/10.1147/sj.342.0185
Autor:
M. Tsao, B. J. Nathanson, Douglas J. Joseph, Bulent Abali, Peter H. Hochschild, Craig B. Stunkel, Monty M. Denneau, P. R. Varker, Dennis G. Shea
Publikováno v:
IPPS
IBM's recently announced Scalable POWERparallel family of systems is based upon the Vulcan architecture, and the currently available 9076 SP1 parallel system utilizes fundamental Vulcan technology. The experimental Vulcan parallel processor is design
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::108ac25e8430847ca867391576c0655b
https://doi.org/10.1109/ipps.1994.288290
https://doi.org/10.1109/ipps.1994.288290
Autor:
Indira Nair, Geert Janssen, Martin Ohmacht, A. Wang, Thomas M. Gooding, B. J. Nathanson, M. Schaal, Burkhard Steinmacher-Burow
Publikováno v:
IBM Journal of Research and Development. 57:7:1-7:12
The memory subsystem of the IBM Blue Gene®/Q Compute chip features multi-versioning and access conflict detection. Its ordered and unordered transaction modes implement both speculative execution (SE) and transactional memory (TM). Blue Gene/Q's lar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b95fb3192ba3af57db87cac9148db36
https://doi.org/10.1147/jrd.2012.2228092
https://doi.org/10.1147/jrd.2012.2228092