RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology

Autor: Mahoro, R. Logan, Mahender Kumar, Dan Mocuta, Michael A. Gribelyuk, Atsushi Azuma, H. Kimura, B. Dirahoui, J. Zimmerman, Shih-Fen Huang, G. Berg, Ishtiaq Ahsan, Allen H. Gabor, J. Herman, Alvin T. S. Chan, Noah Zamdmer, O. Glushchenkov, Edward P. Maciejewski, K. Miyamoto, Gregory G. Freeman, E. J. Nowak, Sadanand V. Deshpande

Publikováno v: 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in VT and REXT accounts for most of th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f1852d9ccce4505dac9cc08c1772e3ac
https://doi.org/10.1109/vlsit.2006.1705271

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

Autor: S. Subbanna, Huilong Zhu, T. Shinohara, R.-V. Bentum, H. Kuroda, C. Penny, Jay W. Strane, D. McHerron, D. Harmon, D. Zamdmer, Q. Ye, Yoshiaki Toyoshima, Paul D. Agnello, S. Wu, G. Freeman, L. Tsou, Atsushi Azuma, Scott J. Bukofsky, Carl J. Radens, M. Angyal, M. Fukasawa, Effendi Leobandung, Byeong Y. Kim, M. Gerhardt, Y. Tan, L. Su, Tenko Yamashita, Anda Mocuta, I.C. Inouc, Takeshi Nogami, Scott D. Allen, R. Logan, K. Miyamoto, Shih-Fen Huang, Ravikumar Ramachandran, J. Pellerin, A. Ray, Siddhartha Panda, Christine Norris, H.V. Meer, H. Nayakama, Mizuki Ono, Keith Jenkins, J. Heaps-Nelson, Wenjuan Zhu, D. Ryan, Michael A. Gribelyuk, B. Dirahoui, M. Inohara, E. Nowak, I. Melville, S. Lane, T. Ivers, K. Ida, Scott Halle, Ishtiaq Ahsan, M.-F. Ng, Huicai Zhong, H. Harifuchi, S.-K. Ku, N. Kepler, F. Wirbeleit, Emmanuel F. Crabbe, H. Yan, T. Kawamura, Mahender Kumar, A. Nomura, L. K. Wang, F. Sugaya, H. Hichri, Gary B. Bronner, P. O'Neil, K. Miyashita, Michael P. Belyansky, J. Cheng, S.-H. Rhee, Lars W. Liebmann, D. Yoneyama, Dan Mocuta, K. McStay, G. Sudo, Dureseti Chidambarrao

Publikováno v: Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL en

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::19c3a590b7034d81db7315743b8ecea4
https://doi.org/10.1109/.2005.1469238

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