Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing

Autor: Patrick Girard, Marcello Traiola, Arnaud Virazel, B. Deveautour

Publikováno v: IEEE 27th International Symposium on
Testing and Robust System Design (IOLTS 2021)
Testing and Robust System Design (IOLTS 2021), Jun 2021, Torino, Italy. pp.1-7, ⟨10.1109/IOLTS52814.2021.9486699⟩
IOLTS

International audience; Until recently, Approximate Computing (AxC) was considered to be a trend topic mainly for resilient applications. Its use aimed at reducing area and power consumption of Integrated Circuits (ICs) at the cost of a reduced accur

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9b7b7753ce0b0f459fe9c5f903a93a78
https://hal-lirmm.ccsd.cnrs.fr/lirmm-03380025

QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction

Autor: Arnaud Virazel, Marcello Traiola, Patrick Girard, B. Deveautour

Publikováno v: ETS
ETS 2020-IEEE European Test Symposium
ETS 2020-IEEE European Test Symposium, May 2020, Tallinn, Estonia. pp.1-6, ⟨10.1109/ETS48528.2020.9131574⟩
IEEE European Test Symposium (ETS)
IEEE European Test Symposium (ETS), May 2020, Tallinn, Estonia. pp.1-6, ⟨10.1109/ETS48528.2020.9131574⟩

International audience; In the last decade, Approximate Computing has become a trend topic for several error tolerant applications. In this context, the use of such paradigm for reducing the area and power cost of conventional fault tolerant schemes

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::389655155278da54198a20a565f6a885
https://doi.org/10.1109/ets48528.2020.9131574

Is aproximate computing suitable for selective hardening of arithmetic circuits?

Autor: S. Pravossoudovitch, Arnaud Virazel, B. Deveautour, Valentin Gherman, Patrick Girard

Publikováno v: 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)
13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Apr 2018, Taormina, Italy. pp.1-6, ⟨10.1109/DTIS.2018.8368559⟩
2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)
DTIS 2018-13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era
DTIS 2018-13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. pp.1-6, ⟨10.1109/DTIS.2018.8368559⟩
DTIS

International audience; Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. In this paper, we address the problem of selective hardening of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::82fbddea1c9c9bde6762f95aabc818e0
https://hal-lirmm.ccsd.cnrs.fr/lirmm-03130537

A low-cost susceptibility analysis methodology to selectively harden logic circuits

Autor: Alberto Bosio, B. Deveautour, Patrick Girard, Imran Wali, M. Sonza Reorda, Arnaud Virazel

Publikováno v: ETS

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art susceptibility estimation methods makes it unscalable with d

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fae578f60b083924b66a4f618d99da04
http://hdl.handle.net/11583/2650514

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