Zobrazeno 1 - 10
of 69
pro vyhledávání: '"B. Dal'zotto"'
Publikováno v:
Microelectronic Engineering. :149-156
As technology moves below 0.1 µm, new applications involving high-resolution exposure tool like ebeam and new materials such as low k dielectric or copper are needed. To prevent contamination from these materials, silicon substrate is encapsulated w
A 0.10 μm buried p-channel MOSFET with through the gate boron implantation and arsenic tilted pocket
Autor:
Christian Caillat, P. Mur, M. Heitzmann, B. Dal’zotto, M.E. Nier, Simon Deleonibus, S. Tedesco, G. Guegan
Publikováno v:
Solid-State Electronics. 46:343-348
Designs of 0.10 μm buried p-channel devices have been studied and compared. We demonstrate that silicon p-MOSFETs with n-type polysilicon gate could achieve a good control of short channel effects. Based on new channel design optimisation using thro
Autor:
G. Lecarval, J.L. Dichiaro, M. Heitzmann, A.M. Papon, P. Mur, F. Jourdan, Christian Caillat, F. Allain, François Martin, M.E. Nier, P. Fugier, B. Dal’zotto, Simon Deleonibus, Alain Toffoli, G. Guegan, Bernard Previtali, S. Tedesco, S. Biswas
Publikováno v:
Solid-State Electronics. 46:349-352
Autor:
Laurent Pain, V. Jaubert, B. Dal’zotto, M. Fayolle, Yves Morand, G Fanget, S. Tedesco, L. Mollard, C Comboroure
Publikováno v:
Microelectronic Engineering. :269-275
Today, the limiting factor for device performance is the transition time of a signal in an IC. A key challenge for 0.1-μm technology is the interconnect delay, which can be reduced by the introduction of low- k dielectric and copper. The integration
Autor:
Denis Mariolle, P. Mur, T. Charvolin, M. Heitzman, L. Palun, D. Fraboulet, François Martin, B. Dal'Zotto, F. Tardif, S. Tedesco, M.E. Nier
Publikováno v:
Microelectronic Engineering. 53:167-170
This paper describes the successive fabrication steps on 8'' wafers of a silicon Single Electron Transistor (SET) using hybrid (e-beam/DUV) lithography. This process is compatible with Silicon On Insulator MOSFET technology, and opens a way to fabric
Autor:
M. Zelsmann, Min, E. Picard, Min, T. Charvolin, Min, E. Hadji, Min, M. Heitzmann, Min, B. Dal'zotto, Min, M.E.Nier, Min, C. Seassal, Min, P. Rojo-Romeo, Min, X. Letartre
Publikováno v:
Journal of Applied Physics; 2/1/2004, Vol. 95 Issue 3, p1606-1608, 3p, 1 Diagram, 2 Graphs
Publikováno v:
Microelectronic Engineering. 30:459-462
In this paper, we present a 0.10 μm NMOS process to achieve devices with reduced short channel effect (SCE) and good current drive capability. Full compatible Chemical Amplified Resist (CAR) process between DUV and e-beam lithography allowed us to u
Publikováno v:
Journal of Magnetism and Magnetic Materials. :1708-1710
Arrays of Si dots 400 nm squares with a spacing of 100 nm and a height of 200 nm were patterned on silicon substrates by electron beam lithography and reactive ion etching, and a Co/Pt multilayer was sputter-deposited on these patterned silicon subst
Publikováno v:
Microelectronic Engineering. 17:75-78
Combination of both phase-shifting mask technology and single layer top-imaging resist will allow deep-UV lithography to meet respectively 256 Mbit requirements and beyond. Using phase-shifting mask in conjunction with PRIME process, 0.175 μm lines
Autor:
Christian Caillat, S. Biswas, G. Lecarval, B. Dal'zotto, G. Guegan, P. Mur, D. Souil, M.E. Nier, M. Heitzmann, François Martin, Simon Deleonibus, A.M. Papon, S. Tedesco
Publikováno v:
IEEE Electron Device Letters. 21:173-175
We have demonstrated the feasibility of 20-nm gate length NMOSFET's using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick. We have achieved devices with real N/sup -/ arsenic implanted extensions and BF/sub 2/ pockets. The devi