Zobrazeno 1 - 2
of 2
pro vyhledávání: '"B. A. Zoric"'
Autor:
J. Keaty, Joachim Gerhard Clabes, C. J. Kircher, Phillip J. Restle, John George Petrovick, James D. Warnock, Carl J. Anderson, B. A. Zoric, Byron L. Krauter
Publikováno v:
IBM Journal of Research and Development. 46:27-51
The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a024e2dbfee5ce608b1811134c6844a8
https://doi.org/10.1147/rd.461.0027
https://doi.org/10.1147/rd.461.0027
Autor:
John George Petrovick, Jack DiLullo, Carl J. Anderson, J. Keaty, Joachim Gerhard Clabes, Shao-Fu S. Chu, P. E. Dudley, James D. Warnock, J. Wagoner, G. Nussbaum, S. Weitzel, B. A. Zoric, R. Weiss, G. Plum, Steve Runyon, Byron L. Krauter, Bradley McCredie, Pong-Fei Lu, S. Schmidt, Michael R. Scheuermann, Phillip J. Restle, Craig R. Carter, J. LeBlanc, J.M. Tendier, P. Harvey
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dad8d8143abf2e20d495527032da1d11
https://doi.org/10.1109/isscc.2001.912617
https://doi.org/10.1109/isscc.2001.912617