Zobrazeno 1 - 10
of 6 150
pro vyhledávání: '"B. A. Baliga"'
Autor:
Aditi Agarwal, B. J. Baliga
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 10, Pp 245-255 (2022)
Significant impact of the ion-implant straggle of the P+ shielding region on the static and dynamic characteristics of 1.2 kV 4H-SiC power MOSFETs is demonstrated in this paper by using analytical and TCAD modeling. The P+ region ion-implant straggle
Externí odkaz:
https://doaj.org/article/ed9e7284fa3e4a0ab11bb262257f7be9
Publikováno v:
News India Times; 9/21/2024, Vol. 55 Issue 38, p14-14, 3/4p
Autor:
Herner, Michael J.
Publikováno v:
Management Revue, 1990 Jan 01. 1(2), 166-171.
Externí odkaz:
https://www.jstor.org/stable/41782193
Autor:
B. Shantharam Baliga, Shrikala Baliga, Animesh Jain, Naveen Kulal, Manu Kumar, Naren Koduvattat, B. G. Prakash Kumar, Arun Kumar, Susanta K. Ghosh
Publikováno v:
Malaria Journal, Vol 20, Iss 1, Pp 1-14 (2021)
Abstract Background Malaria control system (MCS), an Information technology (IT)-driven surveillance and monitoring intervention is being adopted for elimination of malaria in Mangaluru city, Karnataka, India since October 2015. This has facilitated
Externí odkaz:
https://doaj.org/article/5de7caa573d345b9a74234cdb0ebde6c
Autor:
Aditi Agarwal, B. Jayant Baliga
Publikováno v:
Power Electronic Devices and Components, Vol 2, Iss , Pp 100008- (2022)
SiC JBSFETs are fabricated using low contact anneal temperature to simultaneously form the ohmic contact to the N+ source region and a Schottky contact at the JBS diode. It is demonstrated in this paper that a larger N+ source contact width can subst
Externí odkaz:
https://doaj.org/article/c51080c8b8d9414e81ba172b123cf7cd
Autor:
Aditi Agarwal, B. J. Baliga
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 9, Pp 324-333 (2021)
Experimental results obtained for 2.3 kV SiC planar-gate power JBSFETs with different cell topologies are analyzed in this article using analytical models and numerical simulations. All the accumulation-channel devices were simultaneously manufacture
Externí odkaz:
https://doaj.org/article/bb4442acd0c143eda924fea1cf19e92e
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 9, Pp 79-88 (2021)
A 27 nm gate oxide thickness has been successfully used for manufacturing high performance 650V 4H-SiC planar-gate, inversion-channel power JBSFETs in a 6-inch commercial foundry with three (Linear, Hexagonal, and Octagonal) cell topologies. The 27 n
Externí odkaz:
https://doaj.org/article/827d9af738d74fa2bd18f2dbbe318a4b
Autor:
Ajit Kanale, B. Jayant Baliga
Publikováno v:
IEEE Access, Vol 9, Pp 70039-70047 (2021)
The BaSIC(DMM) topology has been experimentally demonstrated to improve the short-circuit time for a 1.2 kV SiC power MOSFET product from $4.8~\mu \text{s}$ to $7.9~\mu \text{s}$ with a 17% increase in on-state resistance by utilizing a commercially
Externí odkaz:
https://doaj.org/article/42529fda9f2a4448823a8e9f06967019
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 499-504 (2020)
2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with
Externí odkaz:
https://doaj.org/article/b633b00133a24ef9be2bd379545e8c53
Autor:
B. Jayant Baliga
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 1111-1117 (2020)
A third-generation PRESiCE™ technology has been qualified for manufacturing SiC power devices in a commercial foundry using 6 inch wafers. JBS diodes, power MOSFETs, and JBSFETs with 1.2 kV ratings were fabricated using this technology with good yi
Externí odkaz:
https://doaj.org/article/25fa898b40bf4930bc427aa85a5f2862