Zobrazeno 1 - 10
of 29
pro vyhledávání: '"B M, Prabhu"'
Object Detection and Classification Framework for Analysis of Video Data Acquired from Indian Roads.
Autor:
Padia, Aayushi, T. N., Aryan, Thummagunti, Sharan, Sharma, Vivaan, K. Vanahalli, Manjunath, B. M., Prabhu Prasad, G. N., Girish, Kim, Yong-Guk, B. N., Pavan Kumar
Publikováno v:
Sensors (14248220); Oct2024, Vol. 24 Issue 19, p6319, 21p
Autor:
Prasad, B. M. Prabhu1 (AUTHOR) prabhu.cs15f10@nitk.edu.in, Parane, Khyamling1 (AUTHOR), Talawar, Basavaraj1 (AUTHOR)
Publikováno v:
Computing. Aug2021, Vol. 103 Issue 8, p1791-1813. 23p.
Autor:
B M Thippeswamy, Mohammed Ghouse, Adugna Deksiso, B M Prabhu Prasad, T C Pramod, B N Pavan Kumar
Publikováno v:
2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT).
Publikováno v:
2022 International Conference on Electrical, Computer and Energy Technologies (ICECET).
Autor:
Thippeswamy, B. M., Ghouse, Mohamed, Ahmed Jafarabad, Shanawaz, Khan Mohammed, Murtuza Ahamed, Adere, Ketema, B. M., Prabhu Prasad, B. N., Pavan Kumar
Publikováno v:
Applied System Innovation (ASI); Apr2023, Vol. 6 Issue 2, p37, 11p
Publikováno v:
Wireless Personal Communications. 114:3295-3319
The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the overall
Publikováno v:
Circuits, Systems, and Signal Processing. 39:5247-5271
In multi-processor system-on-chips, on-chip interconnection plays a significant role. The type of on-chip architecture being used in an application decides the performance of that application. Hence, a quick and versatile network-on-Chip (NoC) simula
Publikováno v:
2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).
Publikováno v:
International Journal of System Assurance Engineering and Management. 10:696-712
Fast simulations are critical in reducing time to market in chip multiprocessors and system-on-chips. Several simulators have been used to evaluate the performance and power consumed by network-on-chips (NoCs). To speedup the simulations, it is neces
Publikováno v:
Computing.
A major role is played by Modeling and Simulation platforms in development of a new Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become slow when simulating thousands of cores on a single chip. FPGAs have become