Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Aymen Ben Hammadi"'
Publikováno v:
Sensors, Vol 24, Iss 7, p 2237 (2024)
This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses lo
Externí odkaz:
https://doaj.org/article/c1f99ea1ef3547d9893a2ff9e9eb32cd
Publikováno v:
2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS).
Publikováno v:
BioNanoScience. 11:390-400
This paper presents a wide tuning-range LC-tank voltage controlled oscillator (VCO). To perform large frequency tuning range, the proposed circuit topology uses a tunable active inductor (TAI) for the coarse frequency tuning, while the fine-tuning is
Publikováno v:
Microelectronics Reliability
Microelectronics Reliability, 2022, 129, pp.114445. ⟨10.1016/j.microrel.2021.114445⟩
Microelectronics Reliability, 2022, 129, pp.114445. ⟨10.1016/j.microrel.2021.114445⟩
International audience
Publikováno v:
Analog Integrated Circuits and Signal Processing. 93:265-275
This paper presents a novel Time-to-digital converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential del
Publikováno v:
ICM
An AD-PLL with a self-calibrated hierarchical Time to Digital Converter (TDC) is proposed to attain a wide range of operation and a phase error monitor to reduce the process lock. To cover a wide range of frequency with improved spectral purity, two
Publikováno v:
IETE Journal of Research. 62:265-273
This paper presents a new topology for realizing a single-ended inductor employing a minimum number of passive components. The active inductor achieves a high quality factor of 895 over a frequency range of 1700 MHz. Its self-resonance frequency is 5
Publikováno v:
SSD
In this paper, a sub-10 ps resolution, high precision and low power consumption Time-to-Digital Converter (TDC) is presented. The proposed TDC is based on the gateable pseudo-delay ring oscillator (GRO) architecture able to reach high linearity and w
Publikováno v:
SSD
This paper presents a high-speed topology for phase counter in an All-digital phase-locked loop (ADPLL) architectures. The structure, called Variable Phase Accumulator (VP AC) is a digital block running at the highest frequency in the ADPLL. The high