Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks

Autor: Aymane Bouzafour, Marc Renaudin, Wendelin Serwe, Radu Mateescu

Publikováno v: MARS 2020-4th Workshop on Models for Formal Analysis of Real Systems
MARS 2020-4th Workshop on Models for Formal Analysis of Real Systems, 2020, Dublin, Ireland. pp.200-239, ⟨10.4204/EPTCS.316.8⟩
MARS@ETAPS

Asynchronous circuits have several advantages for security applications, in particular their good resistance to attacks. In this paper, we report on experiments with modeling, at various abstraction levels, a patented asynchronous circuit for detecti

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::135208a7c7287e77f15e54a93582eaf8
https://hal.inria.fr/hal-02559125

Model-checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

Autor: Aymane Bouzafour, Radu Mateescu, Hubert Garavel, Wendelin Serwe, Marc Renaudin

Publikováno v: ASYNC'18-24th IEEE International Symposium on Asynchronous Circuits and Systems
ASYNC'18-24th IEEE International Symposium on Asynchronous Circuits and Systems, May 2018, Vienne, Austria
ASYNC

International audience; Asynchronous circuits have key advantages in terms of low energy consumption, robustness, and security. However , the absence of a global clock makes the design prone to deadlock, livelock, synchronization, and resource-sharin

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a93e0f694124eb5137da95c47d742502
https://hal.inria.fr/hal-01777093/file/Bouzafour-Renaudin-Garavel-et-al-18.pdf