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of 43
pro vyhledávání: '"Awasthi, Manu"'
Traditional computers with von Neumann architecture are unable to meet the latency and scalability challenges of Deep Neural Network (DNN) workloads. Various DNN accelerators based on Conventional compute Hardware Accelerator (CHA), Near-Data-Process
Externí odkaz:
http://arxiv.org/abs/2208.05294
In this paper, we propose a 'full-stack' solution to designing high capacity and low latency on-chip cache hierarchies by starting at the circuit level of the hardware design stack. First, we propose a novel Gain Cell (GC) design using FDSOI. The GC
Externí odkaz:
http://arxiv.org/abs/2110.01208
In this paper, we propose Zero Aware Configurable Data Encoding by Skipping Transfer (ZAC-DEST), a data encoding scheme to reduce the energy consumption of DRAM channels, specifically targeted towards approximate computing and error resilient applica
Externí odkaz:
http://arxiv.org/abs/2105.07432
Today, almost all computer systems use IEEE-754 floating point to represent real numbers. Recently, posit was proposed as an alternative to IEEE-754 floating point as it has better accuracy and a larger dynamic range. The configurable nature of posit
Externí odkaz:
http://arxiv.org/abs/2104.04763
Autor:
Singh, Sarabjeet, Awasthi, Manu
In this paper we provide a comprehensive, memory-centric characterization of the SPEC CPU2017 benchmark suite, using a number of mechanisms including dynamic binary instrumentation, measurements on native hardware using hardware performance counters
Externí odkaz:
http://arxiv.org/abs/1910.00651
Recently, the capital expenditure of flash-based Solid State Driver (SSDs) keeps declining and the storage capacity of SSDs keeps increasing. As a result, all-flash storage systems have started to become more economically viable for large shared stor
Externí odkaz:
http://arxiv.org/abs/1809.05928
Publikováno v:
In BenchCouncil Transactions on Benchmarks, Standards and Evaluations October 2021 1(1)
Akademický článek
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Autor:
Awasthi, Manu
In recent years, a number of trends have started to emerge, both in microprocessor and application characteristics. As per Moore's law, the number of cores on chip will keep doubling every 18-24 months. International Technology Roadmap for Semiconduc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f7f784f3023f192b1acb1311a9aeaa9
Publikováno v:
MobiCom: International Conference on Mobile Computing & Networking; 2018, p774-776, 3p