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pro vyhledávání: '"Aviles, Robert S."'
This paper proposes an algorithm for synthesis of clock-follow-data designs that provides robustness against timing violations for RSFQ circuits while maintaining high performance and minimizing area costs. Since superconducting logic gates must be c
Externí odkaz:
http://arxiv.org/abs/2409.04944
Autor:
Aviles, Robert S., Beerel, Peter A.
Adiabatic Quantum-Flux-Parametron (AQFP) logic is a promising emerging device technology with six orders of magnitude lower power than CMOS. However, AQFP is challenged by the fact that every gate must be clocked, where proper data transfer requires
Externí odkaz:
http://arxiv.org/abs/2401.07393
A key distinguishing feature of single flux quantum (SFQ) circuits is that each logic gate is clocked. This feature forces the introduction of path-balancing flip-flops to ensure proper synchronization of inputs at each gate. This paper proposes a po
Externí odkaz:
http://arxiv.org/abs/2401.06411