Zobrazeno 1 - 10
of 112
pro vyhledávání: '"Average memory access time"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:2197-2209
To improve the performance of SRAM in caches under near-threshold voltages, several timing speculation techniques, such as the cross-sensing SRAM (CS-SRAM), are proposed. Meanwhile, for a given process, voltage, and temperature (PVT) condition, CS-SR
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18d9e56ce2124734968f3ebe3e5625eb
https://doi.org/10.1109/tvlsi.2021.3120653
https://doi.org/10.1109/tvlsi.2021.3120653
Publikováno v:
Journal of Computer Science and Technology. 36:71-89
Accesses Per Cycle (APC), Concurrent Average Memory Access Time (C-AMAT), and Layered Performance Matching (LPM) are three memory performance models that consider both data locality and memory assess concurrency. The APC model measures the throughput
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c76f452d0a51a6477e00376dafa8077f
https://doi.org/10.1007/s11390-021-0771-8
https://doi.org/10.1007/s11390-021-0771-8
Autor:
Hemangee K. Kapoor, Sukarn Agarwal
Publikováno v:
ACM Transactions on Embedded Computing Systems. 20:1-27
Non-Volatile Memory technologies are coming as a viable option on account of the high density and low-leakage power over the conventional SRAM counterpart. However, the increased write latency reduces their chances as a substitute for SRAM. To attenu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44e21bc0cc82aa81a7460752447dc2be
https://doi.org/10.1145/3411368
https://doi.org/10.1145/3411368
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:4669-4682
Current DRAM-based memory systems face the scalability challenges in terms of memory density, energy consumption, and monetary cost. Hybrid memory architectures composed of emerging nonvolatile memory (NVM) and DRAM is a promising approach to large-c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ae1a9168ba650b4863483ee5d8a20d7
https://doi.org/10.1109/tcad.2020.2966482
https://doi.org/10.1109/tcad.2020.2966482
Autor:
Xiaoyang Zeng, Wei Zhu
Publikováno v:
Algorithms, Vol 14, Iss 176, p 176 (2021)
Algorithms
Volume 14
Issue 6
Algorithms
Volume 14
Issue 6
Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d99e11d3fa650ee20f7ac33bdb045f13
https://www.mdpi.com/1999-4893/14/6/176
https://www.mdpi.com/1999-4893/14/6/176
Autor:
M. Talha Imran, Ivan Puddu, Hasan Al Maruf, Aasheesh Kolli, Irina Calciu, Sanidhya Kashyap, Onur Mutlu
Publikováno v:
ASPLOS
Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bec37784ecb3c65fd056c64c895f1d51
https://doi.org/10.1145/3445814.3446713
https://doi.org/10.1145/3445814.3446713
Publikováno v:
PACT
Reducing the average memory access time is crucial for improving the performance of applications running on multicore architectures. With workload consolidation this becomes increasingly challenging due to shared resource contention. Techniques for p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2ef02b67229de154845bfa77cd1cc0d7
With the increase in processing cores performance have increased, but energy consumption and memory access latency have become a crucial factor in determining system performance. In tiled chip multiprocessor, tiles are interconnected using a network
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bf77cc81f12ded5d7d1fa53bb39c2cf5
http://hdl.handle.net/20.500.11769/371944
http://hdl.handle.net/20.500.11769/371944
Publikováno v:
LASCAS
The development of computing systems, data analytics, and storages for big data computing has resulted in an increasing need for low-power computational platforms and high-performance efficiency, capable of adjusting the processing capability and sto
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47d575fdddca55211620b03cd0985d83
https://doi.org/10.1109/lascas45839.2020.9069014
https://doi.org/10.1109/lascas45839.2020.9069014
Autor:
Yuhang Liu, Xian-He Sun
Publikováno v:
IEEE Transactions on Big Data. 4:273-288
Big data applications demand a better memory performance. Data Locality has been the focus of reducing data access delay. Data access concurrency, however, has become prevalent in modern memory systems in recent years. How to extend existing locality
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9179b004f31c7a3fa61d1d626bd3bca
https://doi.org/10.1109/tbdata.2017.2753825
https://doi.org/10.1109/tbdata.2017.2753825