Zobrazeno 1 - 10
of 204
pro vyhledávání: '"Auvergne, D."'
Publikováno v:
Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)
Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a closed form m
Externí odkaz:
http://arxiv.org/abs/0710.4760
Autor:
Azémard, N. *, Auvergne, D.
Publikováno v:
In Journal of Systems Architecture 2001 47(3):375-382
Publikováno v:
Journal of Applied Physics; Jun1975, Vol. 46 Issue 6, p2683-2689, 7p
Autor:
Ousset, M., Auvergne, D.
Publikováno v:
Ousset, M. ; Auvergne, D. (1994) Analytical delay model for Gallium Arsenide digital circuits. In: Gallium Arsenide Applications Symposium. GAAS 1994, 28-30 April 1994, Turin, Italy.
We present in this paper an analytical method for the evaluation of the performances of the BFL (Buffered FET Logic configuration) GaAs structures. Based on a representation of the average imbalance current, it allows direct evaluation of delays, wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bfc361d334912bc33f2ff80a337e793f
http://amsacta.unibo.it/1836/
http://amsacta.unibo.it/1836/
Publikováno v:
Proceedings of the Conference: Design, Automation & Test in Europe; 3/7/2005, Vol. 1, p640-645, 6p
Autor:
Turgis, S., Auvergne, D.
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Nov98, Vol. 17 Issue 11, p1090. 9p.
Publikováno v:
ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705); 2003, p595-598, 4p
Publikováno v:
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002 (ICMTS 2002); 2002, p41-44, 4p
Publikováno v:
Proceedings of the 28th European Solid-State Circuits Conference; 2002, p727-730, 4p
Publikováno v:
Proceedings 2002 Design, Automation & Test in Europe Conference & Exhibition; 2002, p316-321, 6p