Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Atul Katoch"'
Autor:
Jonathan Chang, Frank Wu, Jung-Ping Yang, Mikan Jr Donald G, Ching-Wei Wu, H. J. Liao, Atul Katoch, Bryan Sheffield, Hau-Tai Hsieh, Hank Cheng, Michael Clinton, Arun Achyuthan, Robin Lee, Johnny Yang
Publikováno v:
ISSCC
Mobile applications, such as smartphones streaming HD videos or virtual-reality headsets rendering 3D landscapes, need SRAM memories that can be put in a low-power state to extend battery life, but can also offer high performance operation when requi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83024d57abcb58115edd5a832287bf6c
https://doi.org/10.1109/isscc.2017.7870335
https://doi.org/10.1109/isscc.2017.7870335
Autor:
C.Y. Pai, W.H. Kuo, Shou-Gwo Wuu, I.F. Wang, Sreedhar Natarajan, M. J Wang, H.Y. Hwang, H.W. Chin, H. F. Lee, K.C. Tu, K.C. Tzeng, Y.W. Ting, Chia-Cheng Chen, Atul Katoch, L.C. Tran, Kuo-Chin Huang, Chung-Hao Tsai, Chun-Yen Chang, Arun Achyuthan, Ching-Chun Wang, Kuang-Hsin Chen, Cormac Michael O'connell, H.C. Chu, T.H. Hsieh, Chia-Shiung Tsai, W.C. Chiang
Publikováno v:
2011 International Electron Devices Meeting.
This paper presents industry's smallest 0.035um2 high performance embedded DRAM cell with cylinder-type Metal-Insulator-Metal (MIM) capacitor and integrated into 28nm High-K Metal Gate (HKMG) logic technology. This eDRAM memory features an HKMG CMOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08e381b66d952fde10007483fde3063d
https://doi.org/10.1109/iedm.2011.6131608
https://doi.org/10.1109/iedm.2011.6131608
Autor:
C.J. Wang, Atul Katoch, Min-Jer Wang, S. Romanovsky, R. Hsieh, Cormac Michael O'connell, Chin-Yi Huang, Sreedhar Natarajan, P. Chen, Arun Achyuthan, Chuan-Yu Wu
Publikováno v:
ISSCC
From 90 nm and below, SoC integration is reaching the point where it makes technical and economic sense to integrate embedded DRAM (eDRAM) onto a die. While eDRAMs have 2.5x to 4x density compared to SRAMs and have lower soft-error rate they are slow
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::795d7c54514bc3d7748082517555f3c9
https://doi.org/10.1109/isscc.2008.4523161
https://doi.org/10.1109/isscc.2008.4523161
Autor:
Atul Katoch, Harry J. M. Veendrick
Publikováno v:
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
As the technology is scaling, the on-chip supply voltage is also reducing. However, off-chip communication voltage has failed to keep-up with this trend. The main reason for this is that the ICs in a system are designed by various design houses and i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ff91c5566dacf69506fa1b49b8c8365
https://doi.org/10.1109/esscir.2005.1541581
https://doi.org/10.1109/esscir.2005.1541581
Publikováno v:
ISCAS (4)
As the technology scales, the global wire delay becomes a major bottleneck in realizing high performance SOCs. Apart from the technological efforts being made to overcome this problem, it is necessary to develop new circuit design techniques. This pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::631a8a7d868442397608d78d82427399
https://doi.org/10.1109/iscas.2005.1465542
https://doi.org/10.1109/iscas.2005.1465542
Publikováno v:
VLSI Design
As the IC process technology scales the on-chip wiring network becomes denser. Increasing aspect ratios of the on-chip interconnects lead to higher coupling capacitances and ultimately higher cross-talk noise, which degrades signal integrity. In this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa72fe45ab20009c5a49376a2352e5ef
https://doi.org/10.1109/icvd.2005.42
https://doi.org/10.1109/icvd.2005.42
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference.
As the technology scales, on-chip interconnects are becoming more and more narrow while their height is not scaling linearly with their width. This leads to an increase in coupling capacitance with neighbouring wires, resulting in higher crosstalk. I
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c164ca36f0fac976966215a3fa544d3
https://doi.org/10.1109/esscir.2004.1356683
https://doi.org/10.1109/esscir.2004.1356683
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540230953
PATMOS
PATMOS
Coupling capacitances between on-chip wires dominate the power consumption of deep submicron busses. Opposite switching signals on adjacent lines cause additional power to be consumed and cause a crosstalk induced delay. This paper proposes a transit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6404d414a7f13e4224bc85cde1352ef
https://doi.org/10.1007/978-3-540-30205-6_20
https://doi.org/10.1007/978-3-540-30205-6_20
