Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Atul C. Ajmera"'
Autor:
X. Chen, Amos, J. Kim, Michael P. Belyansky, Siddhartha Panda, R. Stierstorfer, C. Baiocco, S. Fang, N. Nivo, J. Widodo, D. Chidambarrao, Ko Young Gun, S.S. Tan, Z. Luo, M. Sherony, N. Edleman, Jae-Eun Park, T. Tjoa, T. Dyer, Atul C. Ajmera, P. Nguyen, J. Yuan, Young Way Teh, W. Gao, O. Kwon
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
Integration of stress proximity technique (SPT) and dual stress liners (DSL) has been demonstrated for the first time. The proximity of stress liner is enhanced by spacer removal after salicidation and before the DSL process. It maximizes the strain
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddc98332dac128138605b0c8d4b6f45d
https://doi.org/10.1109/vlsit.2006.1705216
https://doi.org/10.1109/vlsit.2006.1705216
Autor:
I. Yang, F. Zhang, A. Tilke, P. Wrschka, Y.-H. Lin, J. Lian, P. Nguyen, V. Ramanchandran, Gregory M. Johnson, L.S. Leong, Atul C. Ajmera, A. Ebert, S.O. Kim, H. Zhuang, M.-C. Sun, J.-P. Kim, Andy Cowley, Christopher V. Baiocco, J.-H. Ku, W. Lin, J. Greg Massey, Alvin G. Thomas, M. Naujok, A. Vayshenker, G. Leake, A. Fischer, M. Sherony, E. Kaltalioglu, K. Hooper, Dirk Vietzke, C. Griffin, Y.-W. Teh, W. Gao, J. Sudijohno, Manfred Eller, Randy W. Mann, G. Matusiewicz, Y.K. Siew, T. Schiml, Renee T. Mo, S.-M. Choi, R. Knoefler, W.L. Tan, J. Benedict, T. Pompl, J.-H. Yang, F.F. Jamin, Fernando Guarin, K.C. Park, K.-W. Lee, An L. Steegen, Jae-Eun Park, S. Scheer, V. Klee, D.H. Hong, L. Tai, V. Ku, S.L. Liew
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80b515e6807384d732a1a136ebc7ef9d
https://doi.org/10.1109/iedm.2005.1609267
https://doi.org/10.1109/iedm.2005.1609267
Autor:
Robin Davis, T. Sato, Anita Madan, R. Amos, H. Ng, Z. Luo, James Chingwei Li, Dureseti Chidambarrao, Siddhartha Panda, Jae Gon Lee, Atul C. Ajmera, Brian J. Greene, S. S. Mishra, Judson R. Holt, Oleg Gluschenkov, A. Turansky, K. Rim, Richard Lindsay, Nivo Rovedo, Dominic J. Schepis, Jonghae Kim, Yung Fu Chong
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::940c8dc23192e8339271b806c7a46823
https://doi.org/10.1109/iedm.2005.1609388
https://doi.org/10.1109/iedm.2005.1609388
Autor:
C. Ouyang, Kenneth J. Stein, Tak H. Ning, Philip J. Oldiges, Jin Cai, Keith Jenkins, Atul C. Ajmera, M. Steigerwalt, Ghavam G. Shahidi
Publikováno v:
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
A novel vertical bipolar transistor on SOI is proposed and demonstrated. The transistor operates on the principle that the collector region is fully depleted so that the charge carriers travel laterally towards the collector reachthrough and contact
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b465be714eee19623d8532804fbf4af
https://doi.org/10.1109/vlsit.2002.1015439
https://doi.org/10.1109/vlsit.2002.1015439
Autor:
Fariborz Assaderaghi, D. K. Sadana, Dominic J. Schepis, Atul C. Ajmera, R. Bolam, Werner A. Rausch, Bijan Davari, Ghavam G. Shahidi, Effendi Leobandung, Lawrence F. Wagner, L. Wissel, K. Wu, Harold J. Hovel
Publikováno v:
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
Partially-Depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. This paper first reviews the partially-deplete
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d67457eeea74f0a9da5723a37d5618cd
https://doi.org/10.1109/cicc.1999.777303
https://doi.org/10.1109/cicc.1999.777303
Autor:
R. Bolam, Ghavam G. Shahidi, Atul C. Ajmera, Bijan Davari, Werner A. Rausch, Lawrence F. Wagner, Fariborz Assaderaghi, D. Sankus, Kun Wu, Dominic J. Schepis, Effendi Leobandung
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
This partially-depleted (PD) silicon on insulator (SOI) technology results in 20-35% performance gain over a comparable bulk technology. A number of SOI-unique effects that complicate device and circuit design are discussed, along with possible remed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff77c27b1911bd70da039ea377f85f68
https://doi.org/10.1109/isscc.1999.759337
https://doi.org/10.1109/isscc.1999.759337
Autor:
Atul C. Ajmera, J. Lasky, A. Bryant, M. Coffey, K. Wu, Harold J. Hovel, R. Bolam, F. Assaderaghi, Effendi Leobandung, Jeffrey W. Sleight, Werner A. Rausch, Dominic J. Schepis, Lawrence F. Wagner, Ghavam G. Shahidi, D. K. Sadana, Bijan Davari
Publikováno v:
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
A 0.22 /spl mu/m CMOS on SOI technology, using a nonfully depleted device, is developed. This technology uses the same gate lithography and metallization as a comparable bulk technology, but offers a 20-35% higher performance at the chip level. Furth
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d418c9d1af3fde045666b5ddf70ad35b
https://doi.org/10.1109/vlsit.1999.799317
https://doi.org/10.1109/vlsit.1999.799317
Autor:
Jeffrey W. Sleight, Atul C. Ajmera, Dominic J. Schepis, S. Wu, R. Bolam, Bijan Davari, Effendi Leobandung, Ghavam G. Shahidi, Melanie J. Sherony, Werner A. Rausch, Fariborz Assaderaghi
Publikováno v:
International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
The scalability of SOI CMOS technology into the low voltage high performance regime and its comparison with bulk CMOS technology is presented. Based on ring oscillator performance, the 0.13 /spl mu/m SOI CMOS technology can achieve more than 25% fast
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bc9ab5f464df5dc93b539863c092823
https://doi.org/10.1109/iedm.1998.746384
https://doi.org/10.1109/iedm.1998.746384
Autor:
Fariborz Assaderaghi, D.S. Yee, Effendi Leobandung, Dominic J. Schepis, Ghavam G. Shahidi, R. Bolam, H.-J. Wann, Atul C. Ajmera, Bijan Davari, Lawrence F. Wagner, Werner A. Rausch
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
In this paper we demonstrate the fastest CMOS circuits reported to date. At room temperature the unloaded CMOS inverter delay as low as 7.85 psec is measured. This number drops to 5.5 psec at liquid nitrogen temperature. The devices used in the study
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08f48316c68e533a0b19d82d3d18c21a
https://doi.org/10.1109/iedm.1997.650413
https://doi.org/10.1109/iedm.1997.650413
Autor:
Mukesh Khare, S.H. Ku, Woo-Hyeong Lee, J. Snare, Jeffrey J. Welser, H. Park, Atul C. Ajmera, Dominic J. Schepis, Paul D. Agnello, Percy V. Gilbert, Karl Paul Muller, S.K.H. Fung, Bruce B. Doris
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
High performance SOI CMOS designed for the 100 nm technology node is presented. At 1 V supply voltage, the 33 nm devices give a drive current of 1000 (1100) /spl mu/A//spl mu/m DC (dynamic) for NFET and 445 (457) /spl mu/A//spl mu/m for PFET at an of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6fb860856e1fe9e648cebc300bc54184
https://doi.org/10.1109/iedm.2001.979587
https://doi.org/10.1109/iedm.2001.979587