Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Atsushi Matamura"'
Autor:
Naoaki Nishimura, Preston Birdsong, Markova Mariana Tosheva, Atsushi Matamura, Abhishek Bandyopadhyay, Spirer Adam R, Shaolong Liu
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:3573-3582
A low-power 113-dB SNR, -93-dB total harmonic distortion (THD)+N, digital input Δ Σ-based filter-less Class-D amplifier for wireless headphone applications is presented. This performance is achieved by the following architecture improvements: 1) va
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23219aeeb173e2da5fe125f5ae72fb22
https://doi.org/10.1109/jssc.2021.3100548
https://doi.org/10.1109/jssc.2021.3100548
Autor:
Naoaki Nishimura, Atsushi Matamura, Preston Birdsong, Shaolong Liu, Abhishek Bandyopadhyay, Mariana Markova, Rajeev Morajkar
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::284cd8b414a0944c7719764deb1017ef
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830319
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830319
Autor:
Markova Mariana Tosheva, Preston Birdsong, Naoaki Nishimura, Shaolong Liu, Atsushi Matamura, Spirer Adam R, Abhishek Bandyopadhyay
Publikováno v:
ISSCC
True Wireless Stereo/True Wireless Active-Noise-Canceling (ANC) headphones require low-latency digital-input headphone drivers that consume the lowest possible power to maximize battery life while providing high-fidelity audio playback. Typical headp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c3e11e277a5814afecfd1198ce5734a
https://doi.org/10.1109/isscc42613.2021.9365773
https://doi.org/10.1109/isscc42613.2021.9365773
Publikováno v:
ISCAS
A 2W filterless class-D amplifier using multi-level delta-sigma modulation is presented. LC filters consume large PCB space and add significant system cost, so filterless class-D solutions are preferred for portable applications. In this design, a mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52ebfce3ce44249e8ad6ce793a2be7d0
https://doi.org/10.1109/iscas.2009.5117971
https://doi.org/10.1109/iscas.2009.5117971
Autor:
I. Ryan, R. O'Brien, N. McGuinness, A. Abo, Paul John Morrow, Colin G. Lyden, M. Chamarro, Atsushi Matamura, J. Mansson, P. Ventura, P. Minogue, M. Keane, M. McGranaghan
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A second-order mixed CT SC /spl Delta//spl Sigma/ modulator uses multi-bit feedback to reduce clock-jitter sensitivity. The chip is implemented in 0.18/spl mu/m CMOS using 3.3V I/O devices and achieves 102dB SNR in a 20kHz bandwidth by using chopper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df674afd37e1d525ad90c9e948287769
https://doi.org/10.1109/isscc.2005.1493927
https://doi.org/10.1109/isscc.2005.1493927