Výsledky vyhledávání - "Atsushi Kawasumi"

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Autor: Atsushi Kawasumi, Y. Yamamoto, Shinji Miyano, S. Moriwaki, Toshikazu Suzuki, Hirofumi Shinohara, Takeshi Sakurai

Publikováno v: IEEE Journal of Solid-State Circuits. 48:924-931

Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome thes

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3b6b0f6481320cc569b2436e15526aef
https://doi.org/10.1109/jssc.2012.2237572

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Session 17 overview: SRAM

Autor: Hugh Mair, Atsushi Kawasumi

Publikováno v: ISSCC

Advanced SRAM continues to be one of the critical technology enablers for a wide range of applications - from mobile to high performance servers to the Internet of Everything. Combining the process technologies of FinFET and FD-SOI with advanced circ

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::29910bec992f9044c44b065918c583a4
https://doi.org/10.1109/isscc.2016.7418028

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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme

Autor: Takashi Nakada, Atsushi Kawasumi, Shinobu Fujita, Hiroyuki Hara, Keiko Abe, Junichi Ito, Naoharu Shimomura, Satoshi Takaya, Eishi Arima, Kazutaka Ikegami, Keiichi Kushida, Hiroki Noguchi, Hiroshi Nakamura

Publikováno v: ISSCC

Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing-system performance. Although it is necessary to increase memory capacity to f

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e2eb3a3aae0268b365cbec50b96dea84
https://doi.org/10.1109/isscc.2016.7417942

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A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Autor: Yuki Fujimura, Keiichi Kushida, Y. Takeyama, Fumihiko Tachibana, Tomoaki Yabe, Osamu Hirabayashi, A. Suzuki, Atsushi Kawasumi, Yusuke Niki

Publikováno v: IEEE Journal of Solid-State Circuits. 46:2545-2551

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The timing variation of SA attributable to the random variation of transistor t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::30a2a7221f93accb1196e41228bf143c
https://doi.org/10.1109/jssc.2011.2164294

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A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

Autor: Y. Takeyama, G. Fukano, Osamu Hirabayashi, Tomoaki Yabe, Atsushi Kawasumi, Yuki Fujimura, Akira Katayama, Tadahiro Sasaki, Keiichi Kushida, A. Suzuki

Publikováno v: IEEE Journal of Solid-State Circuits. 44:1192-1198

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::30eb4f34af88733a7707a52f1931f03c
https://doi.org/10.1109/jssc.2009.2014009

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7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Autor: Hiroyuki Hara, Keiichi Kushida, Shinobu Fujita, Junichi Ito, Naoharu Shimomura, Shogo Itai, Satoshi Takaya, Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Atsushi Kawasumi

Publikováno v: ISSCC

Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::44ef3422434cab3ea0e39087d8a1fa23
https://doi.org/10.1109/isscc.2015.7062963

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Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques

Autor: Keiichi Kushida, T. Ochiai, Hiroki Noguchi, Eiji Kitagawa, Ito Junichi, Naoharu Shimomura, Hiroyuki Hara, Chikayoshi Kamata, S. Fujita, Shogo Itai, Atsushi Kawasumi, Keiko Abe, Daisuke Saida, Kazutaka Ikegami, Minoru Amano, Chika Tanaka

Publikováno v: 2014 IEEE International Electron Devices Meeting.

Since it has been difficult to increase clock frequency of processors due to power budget, there is a trend toward increase in number of processor cores and cache capacities (Fig. 1) to improve the processor performance. According to this trend, ther

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d4cc282984e848cb706e17fc28e83dbd
https://doi.org/10.1109/iedm.2014.7047123

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