Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Atsushi Hachisuka"'
Autor:
Akira Yamazaki, Atsushi Hachisuka, Katsumi Dosaka, Tsutomu Yoshihara, Teruhiko Amano, Hideyuki Ozaki, Naoya Watanabe, Hideyuki Noda, Masaru Haraguchi, Kazutami Arimoto, Fukashi Morishita, Setsuos Wake
Publikováno v:
IEICE Transactions on Electronics. :2020-2027
The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2164b4ddefa9f4233c32a65d7e165ef9
https://doi.org/10.1093/ietele/e88-c.10.2020
https://doi.org/10.1093/ietele/e88-c.10.2020
Autor:
Hans Jurgen Mattausch, K. Fujishima, K. Inoue, F. Igaue, A. Amo, Fukashi Morishita, Kenji Anami, M. Kuroiwa, Hideyuki Noda, Atsushi Hachisuka, K. Yamamoto, Tetsushi Koide, Kazutami Arimoto, Katsumi Dosaka, Isamu Hayashi, Tsutomu Yoshihara, S. Soeda
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:245-253
This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b30982676e716a72fcc9dc99993293a
https://doi.org/10.1109/jssc.2004.838016
https://doi.org/10.1109/jssc.2004.838016
Autor:
H. Matsuoka, Atsushi Hachisuka, Hideyuki Noda, K. Shigeta, Kenji Anami, Fukashi Morishita, Isamu Hayashi, A. Amo, M. Niiro, M. Okamoto, T. Gyohten, Tatsuo Kasaoka, Katsumi Dosaka, K. Takahashi, Kazutami Arimoto, H. Shinkawata, T. Yoshihara, K. Fujishima
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:204-212
An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::31bb5c834b4cc5e50f645e3bcab987de
https://doi.org/10.1109/jssc.2004.837986
https://doi.org/10.1109/jssc.2004.837986
Autor:
H. Matsuoka, M. Okamoto, A. Amo, K. Takahashi, Isamu Hayashi, Kazutami Arimoto, Katsumi Dosaka, Tatsuo Kasaoka, Atsushi Hachisuka, K. Shigeta, M. Niiro, Fukashi Morishita, T. Gyohten, H. Shinkawata
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13/spl mu/m low-power process and it achieves 312MHz random cycle operation. Data retention power is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d207d19b5590605443348544d0f08fc
https://doi.org/10.1109/isscc.2004.1332664
https://doi.org/10.1109/isscc.2004.1332664
Autor:
Katsumi Dosaka, A. Amo, Shinya Soeda, Hans Jurgen Mattausch, K. Arinnoto, Atsushi Hachisuka, Tetsushi Koide, M. Kuroiwa, Hideyuki Noda, K. Inoue
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
A 4.5 Mb dynamic ternary CAM (DTCAM) is designed in 0.13 /spl mu/m embedded DRAM technology. A performance of 143 M searches/sec is achieved at a power dissipation of 1.1 W and on a small silicon area of 32 mm/sup 2/. A 3.6-times yield improvement is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f72e3de3b5f8545ab6952cd3cc52b94e
https://doi.org/10.1109/isscc.2004.1332667
https://doi.org/10.1109/isscc.2004.1332667
Autor:
Kaoru Motonami, Yasushi Matsui, N. Tsubouchi, Hideaki Arima, Tomonori Okudaira, Atsushi Hachisuka, Takayuki Matsukawa, T. Ogawa, Yoshinori Okumura
Publikováno v:
International Technical Digest on Electron Devices.
The authors propose a novel stacked capacitor cell with dual cell plate (DCP cell) for 64-Mb DRAMs. The major advantage of this cell is that the dual cell plates completely surround the whole surface of the storage polysilicon, and the storage capaci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5266fbb408655bff0c7c2051e23b0079
https://doi.org/10.1109/iedm.1990.237115
https://doi.org/10.1109/iedm.1990.237115
Autor:
Hideaki Arima, Yoshinori Okumura, N. Tsubouchi, M. Shirahata, Atsushi Hachisuka, Tomonori Okudaira, Takayuki Matsukawa
Publikováno v:
International Technical Digest on Electron Devices.
A novel source-to-drain nonuniformly doped channel (NUDC) MOSFET was investigated theoretically and experimentally. Using an analytical model, it is verified that the mobility of the NUDC MOSFET is increased as compared with that of the conventional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d505bd7f8bf4047bf48bcc5429d6b491
https://doi.org/10.1109/iedm.1990.237149
https://doi.org/10.1109/iedm.1990.237149
Autor:
Katsuya Furue, Yoshihiro Nagura, Hideyuki Ozaki, Fukashi Morishita, Akira Yamazaki, Tatsunori Komoike, Tetsushi Tanizaki, F. Igaue, Atsushi Hachisuka, Y. Taito, Toshinori Morihara, Naoya Watanabe, Katsumi Dosaka, Yoshikazu Morooka, Kazutami Arimoto
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
Embedded DRAM (eDRAM) macros have been proposed as away to achieve the low power and wide bandwidth required by graphic controllers, network systems, and mobile systems. Currently, these applications require a reduction of design turn-around time (TA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7417683b8cb8ee5d171694e2fc4459ef
https://doi.org/10.1109/isscc.2001.912686
https://doi.org/10.1109/isscc.2001.912686
Autor:
S. Wake, Hiroki Shimano, Isamu Hayashi, Akira Yamazaki, M. Kobayashi, Hideyuki Noda, Hideyuki Ozaki, Katsumi Dosaka, Shinya Soeda, J. Ootani, Takeshi Fujino, Atsushi Hachisuka, Naoya Watanabe, Y. Okumura, K. Inoue, Yoshikazu Morooka, Fukashi Morishita, Kazutami Arimoto
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
Advanced 3D graphics (3DG) technology will be used in console game machines, and it is desired to develop a rendering controller chip which can handle real time 3D animation with true colors. Embedded DRAM (eDRAM) technology attracts attention of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::627c0c708dfa177263d2bb2ebe94c109
https://doi.org/10.1109/isscc.2000.839830
https://doi.org/10.1109/isscc.2000.839830
Publikováno v:
Japanese Journal of Applied Physics. 26:68
PZT ceramics with compositions close to PbZrO3 possess many desirable properties for potential applications in pyroelectric and piezoelectric devices. Sintering of rhombohedral ferroelectric Pb(Zr1-x Ti x )O3 ceramics with x=0.04 to 0.3 and their die
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38dc99ed4f2814ec0552624ec0739035
https://doi.org/10.7567/jjaps.26s2.68
https://doi.org/10.7567/jjaps.26s2.68