Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Atsuhiro Suga"'
Autor:
Fumihiko Hayakawa, Atsuhiro Suga
Publikováno v:
CANDAR
In these days embedded system needs Open Source Software (OSS) and open framework like as Open GL/Open CL because of better developing efficiency. This paper shows you about high performance SoC architecture for embedded system. This SoC shows lower
Autor:
M. Kai, M. Kimura, Hideo Miyake, I. Amano, Hiromasa Takahashi, S. Ando, A. Asato, N. Higaki, Taizo Sato, Y. Asada, H. Kubosawa, T. Tsuda, Atsuhiro Suga, S. Mitarai, T. Yoshimura, H. Anbutsu
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1640-1648
We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/enco
Publikováno v:
ASP-DAC
This paper introduces a 51.2Gops, 1.0GB/s-DMA single-chip multi-processor integrating quadruple cores and proposes a new power integrity analysis. Our multi-processor is designed to decode MP@HL streams without any dedicated circuits. To achieve such
Autor:
Hiroshi Okano, Yukihito Kawabe, Atsuhiro Suga, A. Sato, Tetsutaro Hashimoto, Shinichiro Tago, Hideo Miyake, Kenichi Kawasaki, T. Shiota, Yasuki Nakamura, W. Shibamoto, Hiromasa Takahashi, Fumihiko Hayakawa
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A 51.2-GOPS chip multi-processor integrates four 8-way VLIW embedded processors with 1.0 GB/s local-bus direct memory access. This IC completes MPEG2 MP@HL video-stream decoding at 68% of its processor capability without dedicated hardware. The 11.9
Publikováno v:
Proceedings. IEEE Asia-Pacific Conference on ASIC.
An 8-way VLIW embedded multimedia processor is developed in 0.11 /spl mu/m 7-layer Cu/Al metal CMOS process technology. The processor achieved the peak performance of 2132 MIPS/2.1 GFLOPS/4.26 GOPS at 533 MHz. This processor equips 4-way integer and
Autor:
Hiroshi Okano, T. Satoh, Hiroshi Takahashi, M. Saito, H. Utsumi, T. Katayama, T. Saruwatari, Y. Takebe, M. Kimura, M. Tsuji, Hideo Miyake, Atsuhiro Suga, T. Sukemura, Yoshio Hirose
Publikováno v:
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).
A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 /spl mu/m 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating
Autor:
K. Wada, T. Sukemura, Y. Hirose, K. Abe, T. Shiota, M. Kimura, T. Satoh, S. Wakayama, M. Saito, T. Ozawa, T. Okano, Hideo Miyake, A. Sakurai, Yasuki Nakamura, K. Kuwano, Y. Takebe, I. Azegami, Atsuhiro Suga, Hiromasa Takahashi, T. Katayama
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
Performance requirements are soaring for embedded processors, whose demand in multimedia processing is rising now more than ever. Some DSP and media processors satisfy this by means of VLIW architecture. However, for embedded processors, less code, l
Conference
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Conference
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