Zobrazeno 1 - 10
of 63
pro vyhledávání: '"Asynchronous array of simple processors"'
Autor:
Zbigniew Hajduk
Publikováno v:
Integration. 59:31-41
This paper presents a simple implementation method of pipelined asynchronous circuits, suitable for commercial field programmable gate arrays (FPGAs). Contrary to other existing asynchronous design techniques, the presented method does not require th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3a377c73da5f08e2f8a66e6207bdc70
https://doi.org/10.1016/j.vlsi.2017.05.002
https://doi.org/10.1016/j.vlsi.2017.05.002
Autor:
Bevan M. Baas, Emmanuel Adeagbo, Brent Bohnenstiehl, Jon J. Pimentel, Anh T. Tran, Aaron Stillmaker, Bin Liu, Timothy Andreas
Publikováno v:
IEEE Micro. 37:63-69
Many important applications can be expressed as a group of fine-grained interconnected tasks, in which individual tasks require under 100 instructions and little data memory. KiloCore, an array of 1,000 independent processors and 12 memory modules, h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b08d3527fdeb40610775518981b7f376
https://doi.org/10.1109/mm.2017.34
https://doi.org/10.1109/mm.2017.34
Publikováno v:
Nanoelectronic Materials and Devices ISBN: 9789811071904
In this paper, an 8-bit asynchronous wave-pipelined arithmetic logic unit has been modified with set of 8 arithmetic and 12 logical operations. All the internal modules have been modified in order to reduce power and latency by using ASIC semi-custom
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a579b60067aadfe8b404b264f3294866
https://doi.org/10.1007/978-981-10-7191-1_20
https://doi.org/10.1007/978-981-10-7191-1_20
Publikováno v:
IEICE Transactions on Electronics. :1669-1679
SUMMARY This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39024223b7f95bbf6548ce1ad8c5c379
https://doi.org/10.1587/transele.e94.c.1669
https://doi.org/10.1587/transele.e94.c.1669
Autor:
E. Work, Tinoosh Mohsenin, Michael A. Lai, M. Meeuwsen, O. Sattari, Jeremy Webb, R.W. Apperson, Zhiyi Yu, Bevan M. Baas
Publikováno v:
Journal of Signal Processing Systems. 53:243-259
This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP processor calculates DSP applications with high energy-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6887d29d49592e53e372cc32ff39fa60
https://doi.org/10.1007/s11265-008-0162-1
https://doi.org/10.1007/s11265-008-0162-1
Publikováno v:
IEEE Transactions on Applied Superconductivity. 17:490-493
Ultra-high speed microprocessors, clocked at hundreds of Gigahertz, remain the dreams of processor designers and consumers alike. However, such processors would require designs and clocking schemes that differ radically from that of current processor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fd16ef87641c55d45120a2e199c8e7a1
https://doi.org/10.1109/tasc.2007.898145
https://doi.org/10.1109/tasc.2007.898145
Publikováno v:
The Scientific World Journal
The Scientific World Journal, Vol 2015 (2015)
The Scientific World Journal, Vol 2015 (2015)
Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6b10916910544d01ea72ce9ffe1ace82
Publikováno v:
Scopus-Elsevier
Array processors are widespread in real-time systems. In the last ten years phase–locked loops have widely been used in array processors as control devices correcting a clock skew. In this paper new type of floating phase–locked loops for array p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8140d4771ee65a549484a057bc40202e
https://doi.org/10.3182/20060628-3-fr-3903.00021
https://doi.org/10.3182/20060628-3-fr-3903.00021
Autor:
Thi-Thuy Nguyen, Xuan-Tu Tran
Publikováno v:
2014 International Conference on Advanced Technologies for Communications (ATC 2014).
The integration of a variety of IP cores into a single chip to meet the high demand of new applications leads to many challenges in timing issues, especially the interface between different clock domains. Globally Asynchronous, Locally Synchronous (G
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb1855f0be23b61d7e50c1fdbcc3acb9
https://doi.org/10.1109/atc.2014.7043413
https://doi.org/10.1109/atc.2014.7043413