Advanced 3d Design and Technologies for 3-Layer Smart Imager

Autor: Vivet, Pascal, Arnaud, Lucile, Borel, Stephan, Bresson, Nicolas, Assous, Myriam, Nicolas, Stephane, Mauguen, Gaelle, Moreau, Stephane, Altieri Scarpato, Mauricio, Billoint, Olivier, Thuries, Sebastien, Ollier, Eric

Publikováno v: 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 2022, Taiwan, Taiwan. ⟨10.1109/VLSI-TSA54299.2022.9771026⟩

International audience; CMOS Imagers have adopted 3D integration using Back-Side Illumination (BSI) technology, with 2 CMOS layers assembled using Wafer-to-Wafer and advanced Hybrid Bonding technology. Targeting innovative AI and Machine Learning app

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::116a0e3dc02c6db971a1756254656c5e
https://doi.org/10.1109/vlsi-tsa54299.2022.9771026

Electrical and morphological characterization for high integrated silicon interposer and technology transfer from 200 mm to 300mm wafer.

Autor: Sunohara, Masahiro, Miyairi, Ken, Mori, Kenichi, Murayama, Kei, Charbonnier, Jean, Assous, Myriam, Bally, JeanPhilippe, Mourier, Thierry, Minoret, Stephane, Mercier, Denis, Toffoli, Alain, Allain, Fabienne, Martinez, Eugenie, Feldis, Helene, Simon, Gilles, Higashi, Mitsutoshi

Publikováno v: 2013 IEEE 63rd Electronic Components & Technology Conference; 2013, p334-341, 8p

Silicon embedded line integration for high end passive silicon interposer.

Autor: Charbonnier, Jean, Assous, Myriam, Bally, Jean-Philippe, Cuchet, Robert, Mourier, Thierry, Minoret, Stephane, Magis, Thomas, Toffoli, Alain, Allain, Fabienne, Simon, Gilles

Publikováno v: 2013 European Microelectronics Packaging Conference (EMPC); 2013, p1-6, 6p