Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Ashwin H. Shah"'
Autor:
I. Wang, C.E. Lemonds, V.M. Nguyen, B. Chae, Kwok K. Chau, Ashwin H. Shah, K.N. Ruparel, James D. Gallia, H.E. Davis, A. Yee, P. Eyres, S. Swamy, T. Yoshino, K. Moore
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:142-149
A BiCMOS gate array in 0.8- mu m technology with CMOS intrinsic gate delays of 100 ps plus 60 ps/fan-out and BiCMOS intrinsic delays of 200 ps with a 17-ps/fan-out drive factor is discussed. A compact base cell (750 mu m/sup 2//gate) has been designe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4350965f31bf62c2ac6691e9b7b9fa4
https://doi.org/10.1109/4.50296
https://doi.org/10.1109/4.50296
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:1494-1501
A 64-tap FIR (finite-impulse-response) digital filter fabricated in a 0.8- mu m, triple-level interconnect, BiCMOS gate-array technology is discussed. The filter has been tested and is fully functional at 100-MHz sampling rate. These results are obta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed98ac9f5732396217fa0ffe9bed8b48
https://doi.org/10.1109/4.62185
https://doi.org/10.1109/4.62185
Autor:
Ashwin H. Shah
Publikováno v:
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
Over a dozen different cell structures and technologies have been proposed in the past few years to reduce DRAM cell size. Each of the proposals represents a tradeoff between process complexity, cell size and cell perfarmance. This panel will attempt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab103407ad66fb70a34e7b179e1de43b
https://doi.org/10.1109/isscc.1987.1157163
https://doi.org/10.1109/isscc.1987.1157163
Autor:
Sanjay K. Banerjee, Ashwin H. Shah, C.J. Pilch, Gordon P. Pollack, Bao Tran, Pallab K. Chatterjee, R.H. Womack, J. Gallia, Hisashi Shichijo, M. Elahy, William F. Richardson, D. Bordelon, H.E. Davis, Satwinder Malhi, Chu-Ping Wang
Publikováno v:
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89b83baec23a5aeb2dd2ba315c456161
https://doi.org/10.1109/isscc.1986.1156951
https://doi.org/10.1109/isscc.1986.1156951
Autor:
Ping Yang, Ashwin H. Shah
Publikováno v:
Proceedings of International Conference on Microelectronics.
This paper reviews the trends in the MOS technology as we approach the turn of the century and addresses the challenges that we face as the devices geometries continue to scale and as the need for lower power dissipation grows, albeit with the demand
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::451a92570f211549f6a0dcbfbfb40435
https://doi.org/10.1109/icmel.1995.500826
https://doi.org/10.1109/icmel.1995.500826
Autor:
W.R. Hunter, C.C. Rhodes, W.C. Bruncke, Yung-Tao Lin, E.A. Walker, Pallab K. Chatterjee, Ashwin H. Shah
Publikováno v:
IEEE Transactions on Electron Devices. 29:700-706
An alternative method to coordinated scaling of overall device dimensions and structural parameters for increasing the bandwidth of static RAM's is described in this paper. This method recognizes that the signal flow through a SRAM is uniquely determ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d681e901dcaca68ef5feb2f20b37b306
https://doi.org/10.1109/t-ed.1982.20765
https://doi.org/10.1109/t-ed.1982.20765
Autor:
M. Elahy, Pallab K. Chatterjee, Hisashi Shichijo, R.H. Womack, Sanjay K. Banerjee, Ashwin H. Shah
Publikováno v:
IEEE Electron Device Letters. 5:527-530
The leakage current between trench capacitors for megabit dynamic MOS memories has been modeled and studied through simulations. The minimum substrate doping density, to limit the leakage current to 1 pA/µm, has been determined as a function of tren
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::797c320f54de3c52a0f4dd1e3eed0207
https://doi.org/10.1109/edl.1984.26013
https://doi.org/10.1109/edl.1984.26013
Autor:
H. V. Tran, Robert H. Havemann, T.E. Ham, Ashwin H. Shah, P. K. Fung, David B. Scott, Roger A. Haken, Robert H. Eklund
Publikováno v:
IEEE Journal of Solid-State Circuits. 23:1041-1047
The authors describe the first high-performance, high-density ECL SRAM (emitter-coupled-logic static random-access memory) compatible with battery backup techniques. The 256K device has a measured access time of 8 ns. Fabricated in a 0.8- mu m BiCMOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb7ccb9460ed8146703c81f8f9febc10
https://doi.org/10.1109/4.5922
https://doi.org/10.1109/4.5922
Publikováno v:
IEEE Transactions on Electron Devices. 35:108-116
The authors discuss a band-to-band tunneling mechanism in the trench transistor cell (TTC), which is used in Texas Instruments' 4-Mbit DRAM. This effect should be operative in the class of trench cells in which the charge is stored inside the trench
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab2d8612cd22a232c7063776eff86ed9
https://doi.org/10.1109/16.2425
https://doi.org/10.1109/16.2425
Autor:
Hisashi Shichijo, James D. Gallia, Gordon P. Pollack, Satwinder Malhi, B. Tran, R.H. Womack, D.M. Bordelon, H.E. Davis, M. Elahy, Sanjay K. Banerjee, Ashwin H. Shah, Chu-Ping Wang, William F. Richardson, Pallab K. Chatterjee, C.J. Pilch
Publikováno v:
IEEE Journal of Solid-State Circuits. 21:618-626
An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2907e4d5d4aff3458fa16aedf52eae1b
https://doi.org/10.1109/jssc.1986.1052586
https://doi.org/10.1109/jssc.1986.1052586