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of 9
pro vyhledávání: '"Ashok Challa"'
Autor:
Scott Pearson, Paul Collanton, Tirthajyoti Sarkar, Marc Dagan, James Victory, Cristian Andreev, Xiao Yunpeng, Ashok Challa
Publikováno v:
2019 IEEE Applied Power Electronics Conference and Exposition (APEC).
This paper proposes a novel physical approach to corner and statistical SPICE model generation for Shielded-Gate Trench Power MOSFETs. The technique is derived from the mature IC industry standard approach known as Backward Propagation of Variance. P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c64fdd5719913cfbc208f1fb68486b99
https://doi.org/10.1109/apec.2019.8722168
https://doi.org/10.1109/apec.2019.8722168
Publikováno v:
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD).
Physics-based device-circuit co-simulation turns out to be an extremely valuable tool to guide and optimize process technology development and device design for high-performance power MOSFETs. It is particularly well-suited to the need of emerging tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2685a49992babe470f7f7e15c2e1e4f0
https://doi.org/10.1109/ispsd.2018.8393659
https://doi.org/10.1109/ispsd.2018.8393659
Publikováno v:
16th International Workshop on Physics of Semiconductor Devices.
Shielded-gate trench-MOSFETs yield superior performance compared to conventional gate trench devices by allowing higher doping density in the drift region and providing a ‘shielding effect’ for the gate by placing an intermediate electrode betwee
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0182a7d0096d23fa2db224d97069921
https://doi.org/10.1117/12.923768
https://doi.org/10.1117/12.923768
Publikováno v:
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs.
Power MOSFET designs have been moving to higher performance particularly in the medium voltage area. (60V to 300V) New designs require lower specific on-resistance (R SP ) thus forcing designers to push the envelope of increasing the electric field s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13b7a8a91d35c5c4c3c78a0769dce2e0
https://doi.org/10.1109/ispsd.2011.5890814
https://doi.org/10.1109/ispsd.2011.5890814
Publikováno v:
2006 IEEE International Symposium on Power Semiconductor Devices & IC's.
The presented device structure offers novel features of recessed interlevel dielectric (ILD) into the active device trench and perpendicular N+ body design. This allows for the device self alignment and unit size shrink to 1mum and below without comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8534261935cb1a0854b8090569fb0d2d
https://doi.org/10.1109/ispsd.2006.1666081
https://doi.org/10.1109/ispsd.2006.1666081
Publikováno v:
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..
In this paper the development of a novel low voltage PLANAR gate VDMOS device and process is presented. The device architecture was developed to reduce output capacitance while maintaining low on-state resistance for use in power switching applicatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac8f893b48a16f7ee35fb7e97d053c3f
https://doi.org/10.1109/ispsd.2005.1487982
https://doi.org/10.1109/ispsd.2005.1487982
Publikováno v:
MRS Proceedings. 355
The growth morphology of Ag on GaAs (110) surface, at low coverage, is investigated with Monte Carlo simulations using a solid-on-solid model. Experimentally Ag deposited at room temperature forms isotropie islands and forms islands elongated along t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd442cb5d99d2a86cc8c7a221054f269
https://doi.org/10.1557/proc-355-101
https://doi.org/10.1557/proc-355-101
Publikováno v:
Japanese Journal of Applied Physics; June 1990, Vol. 29 Issue: 6 p1097-1097, 1p
Conference
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