Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Ashish Venkat"'
Publikováno v:
IEEE Design & Test. 39:49-57
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fff81ede9e8590aa942dfbc48569d898
https://doi.org/10.1109/mdat.2022.3152633
https://doi.org/10.1109/mdat.2022.3152633
Publikováno v:
IEEE Computer Architecture Letters. 21:89-92
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db586f911a38267c29b5aff12054b5cb
https://doi.org/10.1109/lca.2022.3201168
https://doi.org/10.1109/lca.2022.3201168
Autor:
Logan Moody, Wei Qi, Abdolrasoul Sharifi, Layne Berry, Joey Rudek, Jayesh Gaur, Jeff Parkhurst, Sreenivas Subramoney, Kevin Skadron, Ashish Venkat
Publikováno v:
2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0725a20e954945109c85e74ca462b5f
https://doi.org/10.1109/micro56248.2022.00024
https://doi.org/10.1109/micro56248.2022.00024
Publikováno v:
ISCA
Modern Intel, AMD, and ARM processors translate complex instructions into simpler internal micro-ops that are then cached in a dedicated on-chip structure called the micro-op cache. This work presents an in-depth characterization study of the micro-o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3396c11ac73fe3c90d79e5380e0115a6
https://doi.org/10.1109/isca52012.2021.00036
https://doi.org/10.1109/isca52012.2021.00036
Publikováno v:
ISCA
The rapid influx of biosequence data, coupled with the stagnation of the processing power of modern computing systems, highlights the critical need for exploring high-performance accelerators that can meet the ever-increasing throughput demands of mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a0efd7842e4cc9825d6b44bc7fea98d
https://doi.org/10.1109/isca52012.2021.00028
https://doi.org/10.1109/isca52012.2021.00028
Publikováno v:
IEEE Micro. 39:75-83
Modern instruction set decoders feature translation of native instructions into internal micro-ops to simplify the CPU design and improve instruction-level parallelism. However, this translation is static in most known instances. This paper proposes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ea4eec93447356076f2fb682885a51e
https://doi.org/10.1109/mm.2019.2910507
https://doi.org/10.1109/mm.2019.2910507
Autor:
Ashish Venkat, Rasool Sharifi
Publikováno v:
ISCA
This work introduces the CHEx86 processor architecture for securing applications, including legacy binaries, against a wide array of security exploits that target temporal and spatial memory safety vulnerabilities such as out-of-bounds accesses, use-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd745fa216abb60f8e9e1a55b2eb3094
https://doi.org/10.1109/isca45697.2020.00068
https://doi.org/10.1109/isca45697.2020.00068
Publikováno v:
ISCA
This paper presents Packet Chasing, an attack on the network that does not require access to the network, and works regardless of the privilege level of the process receiving the packets. A spy process can easily probe and discover the exact cache lo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8df115c7d3db23de7b0a7a2dbb0eed62
https://doi.org/10.1109/isca45697.2020.00065
https://doi.org/10.1109/isca45697.2020.00065
Publikováno v:
ASPLOS
This paper describes context-sensitive fencing (CSF), a microcode-level defense against multiple variants of Spectre. CSF leverages the ability to dynamically alter the decoding of the instruction stream, to seamlessly inject new micro-ops, including
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e088f5ff7fb4c3b64ef641f25431294
https://doi.org/10.1145/3297858.3304060
https://doi.org/10.1145/3297858.3304060
Publikováno v:
PMAM@PPoPP
Heterogeneous architectures have become increasingly common. From co-packaging small and large cores, to GPUs alongside CPUs, to general-purpose heterogeneous-ISA architectures with cores implementing different ISAs. As diversity of execution cores g
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2fbe77c46705bf71b18a48055aeadbe
https://doi.org/10.1145/3303084.3309492
https://doi.org/10.1145/3303084.3309492