Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Ashay Rane"'
Autor:
Dinesh Maheshwari, Purushotham Kamath, Dennis Abts, Jonathan Ross, Garrin Kimmell, Andrew Bell, Adrian Macias, Jennifer Hwang, Geert Rosseel, Jon Purdy, Richard Czekalski, Jonathan Sparling, Jeff Werner, Michael Beidler, Max Baker, Evan Laforge, Matt Boyd, Rebekah Leslie-Hurd, Brian Kurtz, Jim Sproch, E. R. Creswick, Temesghen Kahsai, Mahitha Venigalla, Gleb Gagarin, Michael Bye, John F. Thompson, Omar Ahmad, Tom Hawkins, Ashay Rane, Mark Wong-VanHaren, Sahil Parmar
Publikováno v:
ISCA
In this paper, we introduce the Tensor Streaming Processor (TSP) architecture, a functionally-sliced microarchitecture with memory units interleaved with vector and matrix deep learning functional units in order to take advantage of dataflow locality
Publikováno v:
Research in Attacks, Intrusions, and Defenses ISBN: 9783030004699
RAID
RAID
In this work we present, MicroStache, a specialized hardware mechanism and new process abstraction for accelerating safe region security solutions. In the safe region paradigm, an application is split into safe and unsafe parts. Unfortunately, freque
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d79e5b5c80a529164bca951e7d3bb15d
https://doi.org/10.1007/978-3-030-00470-5_17
https://doi.org/10.1007/978-3-030-00470-5_17
Autor:
Ashay Rane, James Browne
Publikováno v:
ACM Transactions on Parallel Computing. 1:1-20
Program performance optimization is usually based solely on measurements of execution behavior of code segments using hardware performance counters. However, memory access patterns are critical performance limiting factors for today's multicore chips
Autor:
Ashay Rane, Rakesh Krishnaiyer, Leonardo Fialho, Zakhar Matveev, James C. Browne, Chris J. Newburn
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783319174723
LCPC
LCPC
Modern compilers execute sophisticated static analyses to enable optimization across a wide spectrum of code patterns. However, there are many cases where even the most sophisticated static analysis is insufficient or where the computation complexity
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::add79dd0bcb2cbea3d6b344fbba38081
https://doi.org/10.1007/978-3-319-17473-0_24
https://doi.org/10.1007/978-3-319-17473-0_24
Autor:
James Browne, Ashay Rane
Publikováno v:
PACT
Program performance optimization is usually based solely on measurements of execution behavior of code segments using hardware performance counters. However, memory access patterns are critical performance limiting factors for today's multicore chips
Publikováno v:
Proceedings of the 1st Conference of the Extreme Science and Engineering Discovery Environment: Bridging from the eXtreme to the campus and beyond.
Heterogeneous architectures (mainstream CPUs with accelerators/co-processors) are expected to become more prevalent in high performance computing clusters. This paper deals specifically with attaining efficient execution on nodes which combine Intel'
Publikováno v:
SC Companion
Graphics Processing Units (GPUs) are a low cost, low power means of exploiting large-scale parallelism. Source-to-source transformation tools for mapping CPU code to GPU code (e.g. PGI Accelerator) are available. But identification of those code segm
Autor:
James Browne, Ashay Rane
Publikováno v:
CLUSTER
Program performance optimization is generally based on measurements of execution behavior of code segments. However, an equally important task for performance optimizations is understanding memory access behaviors and thus, data structure access patt