Výsledky vyhledávání - "Asgar Abbaszadeh"

Low complexity digital background calibration algorithm for the correction of timing mismatch in time-interleaved ADCs

Autor: Asgar Abbaszadeh, Esmaeil Najafi Aghdam, Alfredo Rosado-Muñoz

Publikováno v: Microelectronics Journal. 83:117-125

A low-complexity post-processing algorithm to estimate and compensate for timing skew error in a four-channel time-interleaved analog to digital converter (TIADC) is presented in this paper, together with its hardware implementation. The Lagrange int

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c4b69254a41609749dec7a49c6692d28
https://doi.org/10.1016/j.mejo.2018.11.019

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An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface

Autor: Manuel Bataller-Mompeán, Taras Iakymchuk, Alfredo Rosado-Muñoz, Asgar Abbaszadeh, Jose V. Frances-Villora

Publikováno v: Abbaszadeh, Asgar Iakymchuk, Taras Bataller Mompean, Manuel Francés Villora, José Vicente Rosado Muñoz, Alfredo 2019 An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface Electronics 8 1 94-1 94-20
RODERIC. Repositorio Institucional de la Universitat de Valéncia
instname
Electronics
Volume 8
Issue 1
Electronics, Vol 8, Iss 1, p 94 (2019)

High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the comput

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bb0491dd6d8ee3879779e1e310278171
https://doi.org/10.3390/electronics8010094

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Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

Autor: Asgar Abbaszadeh, Alfredo Rosado-Muñoz, Esmaeil Najafi Aghdam

Publikováno v: Abbaszadeh, Asgar Aghdam, Esmaeil N. Rosado Muñoz, Alfredo 2019 Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC Analog Integrated Circuits and Signal Processing 99 2 299 310
RODERIC. Repositorio Institucional de la Universitat de Valéncia
instname
RODERIC: Repositorio Institucional de la Universitat de Valéncia

Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved chann

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::db45e44837cd093830c3c9ac3df626e8
https://hdl.handle.net/10550/75703

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Efficient realization of reconfigurable FIR filter using the new coefficient representation

Autor: Khosrov Dabbagh Sadeghipour, Asgar Abbaszadeh

Publikováno v: IEICE Electronics Express. 8:902-907

In this paper, efficient reconfigurable finite-impulse response (FIR) filter architecture is presented based on a new coefficient representation method. The proposed binary signed subcoefficient method increases the common subexpressions and decrease

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9a48dc13c6f328535c1fd1537e06d998
https://doi.org/10.1587/elex.8.902

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A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications

Autor: Asgar Abbaszadeh, Khosrov Dabbagh Sadeghipour, Anasystem Azerbaijan

Publikováno v: DSP

Multistandard wireless communication systems require the reconfigurable FIR filters with low complexity architectures. The complexity of FIR filters is dominated by the coefficient multipliers. It is well known that partial product is an efficient te

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::96ea39d338a9148fe9f1c7fe59a892e1
https://doi.org/10.1109/icdsp.2011.6004958

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An efficient postprocessor architecture for channel mismatch correction of time interleaved ADCs

Autor: Asgar Abbaszadeh, Khosrov Dabbagh-Sadeghipour

Publikováno v: 2010 18th Iranian Conference on Electrical Engineering.

A pipelined post-processor architecture is proposed in this paper for digital background calibration of time interleaved ADCs. An adaptive filter technique is used for correction of offset and gain mismatches between ADC channels. Only one calibratio

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::82cf8a8f4e387de62619e1e9157a7d2b
https://doi.org/10.1109/iraniancee.2010.5507040

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A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCS

Autor: Khosrov Dabbagh-Sadeghipour, Asgar Abbaszadeh

Publikováno v: SiPS

A new hardware efficient, low power postprocessor architecture is presented in this paper to correct the mismatch errors in time interleaved ADCs. The Least Mean Squares (LMS) algorithm is utilized as correction algorithm to identify the offset and g

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::48424597d6022051af380f254d6426e5
https://doi.org/10.1109/sips.2009.5336252

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