Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Aseem Gupta"'
Autor:
Lorenzo Rota, Aseem Gupta, Bojan Markovic, Angelo Dragone, Kamath Umanath R, C. Tamma, Aldo Pena-Perez
Publikováno v:
ISCAS
Fast settling, accurate reference voltage buffer (RVB) are one of the key blocks of a successive approximation register (SAR) ADC. This paper presents the design of a RVB, which is aimed to drive SAR ADC architectures with hybrid RC-DAC: a popular im
Autor:
Dionisio Doering, Angelo Dragone, Hussein Ali, Xiaobin Xu, Lorenzo Rota, Aldo Pena-Perez, Savino Petrignani, Aseem Gupta, Bojan Markovic, Faisal Abu-Nimeh, B. Reese, C. Tamma, P. Caragiulo, Kamath Umanath R
Publikováno v:
2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC).
This work describes the primary modules of the digital read-out system implemented in a System-On-Chip (SoC) ASIC optimized for noble liquid Time Projection Chambers (TPCs). The ASIC, referred here as CRYO, performs digital and analog functions and h
Autor:
P. Caragiulo, Dionisio Doering, Xiaobin Xu, Hussein Ali, Bojan Markovic, Kamath Umanath R, M. E. Convery, Faisal Abu-Nimeh, P. A. Breur, Aldo Pena-Perez, Savino Petrignani, Aseem Gupta, Angelo Dragone, C. Tamma, Patrick Tsang, Lorenzo Rota
Publikováno v:
2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC).
CRYO ASIC is a System-On-Chip (SoC) waveform digitizer and serializer for Time Projection Chamber experiments operating at cryogenic temperatures. Implemented in 130 nm CMOS process, this ASIC combines both analog and digital functionalities includin
Autor:
Savino Petrignani, D. Doering, B. Reese, Faisal T. Abu-Nimeh, Aldo Pena-Perez, Pietro Caragiulo, Aseem Gupta, Bojan Markovic, Camillo Tamma, Angelo Dragone, Xiaobin Xu, Lorenzo Rota, Hussein Ali, Kamath Umanath R
Publikováno v:
MWSCAS
This work presents the implementation of the digital read-out architecture of a System-On-Chip (SoC) optimized for Time Projection Chamber (TPC) detectors used in neutrino science. The CRYO ASIC works at cryogenic temperatures and performs signal pre
Autor:
Paul Pop, Aseem Gupta
Publikováno v:
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis.
Autor:
Nikil Dutt, Fadi J. Kurdahi, Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan
Publikováno v:
Conf. Computing Frontiers
Leakage currents in on-chip SRAMs: caches, branch predictor, register files and TLBs, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based stru
Autor:
Fadi J. Kurdahi, Alexander V. Veidenbaum, Houman Homayoun, Nikil Dutt, Avesta Sasan, Aseem Gupta
Publikováno v:
High Performance Embedded Architectures and Compilers ISBN: 9783642115141
HiPEAC
HiPEAC
In order to reduce register file's peak temperature in an embedded processor we propose RELOCATE: an architectural solution which redistributes the access pattern to physical registers through a novel register allocation mechanism. RELOCATE regionali
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e03514fdd2b70ce52487dac6e024c2f9
https://doi.org/10.1007/978-3-642-11515-8_17
https://doi.org/10.1007/978-3-642-11515-8_17
Publikováno v:
2009 International Symposium on VLSI Design, Automation and Test.
In current Systems-on-Chip (SoC) designs, managing peak temperature is critical to ensure operation without failure. Our novel Communication Architecture Based Thermal Management (CBTM) scheme manages thermal behavior of components by delaying the ex
Publikováno v:
2008 14th International Workshop on Thermal Inveatigation of ICs and Systems.
Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we
Publikováno v:
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
Summary form only given. Improvements in the speed and the size of chips due to process scaling come with the penalties of increased power densities and higher operating temperatures. Higher temperature not only poses a risk of thermal runaway of the