Zobrazeno 1 - 10
of 37
pro vyhledávání: '"Arvind Chakrapani"'
Autor:
Arvind Chakrapani
Publikováno v:
IEEE Access, Vol 8, Pp 136617-136637 (2020)
The 3rd Generation Partnership Project (3GPP) specification of the fifth generation (5G) New Radio (NR) allows for a highly scalable and flexible radio access technology to cater to network operators with different requirements. Such scalability and
Externí odkaz:
https://doaj.org/article/3fa9ff5eb3c3409fad42bd4c0812bdae
Autor:
Arun Kumar M., Arvind Chakrapani
Publikováno v:
PLoS ONE, Vol 17, Iss 9 (2022)
Electrocardiograms (ECG) are extensively used for the diagnosis of cardiac arrhythmias. This paper investigates the use of machine learning classification algorithms for ECG analysis and arrhythmia detection. This is a crucial component of a conventi
Externí odkaz:
https://doaj.org/article/d39a4f58d48249ec9b91bbc1fa59286d
Publikováno v:
Computer Systems Science and Engineering. 46:1141-1152
Publikováno v:
Circuits, Systems, and Signal Processing. 41:6530-6546
Publikováno v:
Analog Integrated Circuits and Signal Processing. 110:583-594
Publikováno v:
Circuits, Systems, and Signal Processing. 41:2308-2321
Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performa
Publikováno v:
National Academy Science Letters. 45:165-168
A high performance and energy-efficient 1-bit full adder (FA) circuit is proposed. For circuit validation, Cadence simulation is performed on the proposed and conventional FAs using 45 nm CMOS process technology. The proposed circuit achieves 19.68
Publikováno v:
Circuits, Systems, and Signal Processing. 40:5718-5732
This article presents a high-performance hybrid full adder (HPHFA) designed with static CMOS logic and pass transistor logic to achieve better power delay product (PDP). The circuit was implemented using cadence virtuoso tool on gpdk 90 nm and 45 nm
Autor:
S. Rajendran, Arvind Chakrapani
Publikováno v:
Arabian Journal for Science and Engineering. 46:10281-10286
The level shifters (LSs) are the most significant interfacing circuits in multi-supply mixed-signal systems. This letter presents a high-speed and energy-efficient voltage level shifter with wide-range conversion from sub-threshold to I/O voltage. Th
Autor:
Arvind Chakrapani, S. Rajendran
Publikováno v:
Analog Integrated Circuits and Signal Processing. 107:629-635
The never-ending demands for battery-powered applications are driven by technological advances in the field of low power digital CMOS circuits. The voltage level shifters are crucial primitives for Systems-on-Chip (SoC) applications and systems opera