Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Arul Sendhil"'
Autor:
Manish Jain, C. Huang, Keisuke Saito, Wendemagegnehu T. Beyene, Kun-Yung Ken Chang, J. Wei, Deborah Dressier, T. J. Chin, Catherine Chen, Dave Secker, Phuong Le, Vijay Gadde, Chris Madden, Xingchao Yuan, Ting Wu, Chanh Tran, Mahabaleshwara, Sanku Mukherjee, Navin Kumar Mishra, Ling Yang, Leneesh Raghavan, Arul Sendhil, Amir Amirkhany, Hai Lan, Arun Vaidyanath, R. Schmitt, Gundlapalli Shanmukha Srinivas, Shuaeb Fazeel, Mohammad Hekmat, Kambiz Kaviani, Kapil Vyas, Jie Shen
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:911-925
This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memori
Publikováno v:
VLSI Design
Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the refere
Publikováno v:
VLSI Design
Resetting flip flops in high speed clock domain across wide silicon area is a challenge due to significant delay variations between the clock and reset signals. In this paper, a novel method of transmitting Reset Through the Clock (RTC) tree is propo
Publikováno v:
2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.
While the need for higher graphics memory bandwidth continues to grow, it is evident that owing to the multitude of challenges in single ended signaling, pushing data rates beyond 6 Gbps is exceedingly difficult. To isolate, quantify and combat the m
Publikováno v:
CICC
A bi-modal x32 memory interface supports 6.4-Gbps GDDR5 signaling as well as 2.4-Gbps DDR3 signaling with a 1.5V IO supply. The interface incorporates a novel driver and pre-driver structure that supports one-tap equalization and presents very small
Publikováno v:
VLSI Design
Magnitude of equalization applied by a receiver equalization circuit varies across silicon process and environmental conditions. We propose a novel method to auto calibrate a programmable receiver equalization circuit to a target gain equalization va
Publikováno v:
2015 28th International Conference on VLSI Design; 2015, p204-208, 5p