Zobrazeno 1 - 10
of 73
pro vyhledávání: '"Artur Jutman"'
Publikováno v:
Microelectronics Reliability. 146:115010
This is the first book that sums up test-related modeling of digital circuits and systems by a new structural-decision-diagrams model. The model represents structural and functional information jointly and opens a new area of research.The book introd
Autor:
Elena Ioana Vatajelu, Jaan Raik, Matteo Sonza Reorda, Mehdi B. Tahoori, Maria K. Michael, Artur Jutman, Stephan Eggersgluss, Said Hamdioui
Publikováno v:
IEEE International Test Conference (ITC'2019)
IEEE International Test Conference (ITC'2019), Nov 2019, Washington DC, United States. IEEE
ITC
IEEE International Test Conference (ITC'2019), Nov 2019, Washington DC, United States. pp.1-4, ⟨10.1109/ITC44170.2019.9000148⟩
IEEE International Test Conference (ITC'2019), Nov 2019, Washington DC, United States. IEEE
ITC
IEEE International Test Conference (ITC'2019), Nov 2019, Washington DC, United States. pp.1-4, ⟨10.1109/ITC44170.2019.9000148⟩
International audience; This paper is dedicated to the IEEE European Test Symposium (ETS). It offers an overview of all the European Test Workshop and Symposium events, from its first edition in 1996 to the next edition in 2020.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::251e7241dae7d24e66b5989df932784e
https://hal.archives-ouvertes.fr/hal-02506911
https://hal.archives-ouvertes.fr/hal-02506911
Publikováno v:
Proc. IEEE European Test Symposium 2019 (in press)
ETS
ETS
The increasing number of embedded instruments used to perform test, monitoring, calibration and debug within a semiconductor device has called for a brand new standard—the IEEE 1687. Such a standard resorts to a reconfigurable scan network to provi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::92ce52f0aafe07466b4e84b6346cc9b3
Autor:
Sergei Odintsov, Thomas Wenzel, Artur Jutman, Igor Aleksejev, Sergei Devadze, Heiko Ehrenberg
Publikováno v:
2019 IEEE AUTOTESTCON.
With continually growing adoption of FPGA based designs, and more features and capabilities available in FPGAs, board and system level test applications can - and should - take advantage of FPGA embedded instrumentation. Such FPGA assisted tests not
Publikováno v:
2019 IEEE European Test Symposium (ETS).
Publikováno v:
DDECS
Nowadays, increasing demand for High-Performance Systems produces significant growth in usage of Field Programmable Gate Arrays (FPGAs) for different applications thanks to their flexibility and high level of parallelism. Such systems rely on complex
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::08bdd1ca31ecc56850ad96a422d511e1
http://hdl.handle.net/11583/2735942
http://hdl.handle.net/11583/2735942
Publikováno v:
IEEE Design & Test. 30:26-35
The infrastructure of IJTAG can be utilized during operation to detect errors and make appropriate fault handling. This article describes an architecture where error latency and automation are important requirements.
Autor:
Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Kerkoff, Hans G., Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Publikováno v:
TU Graz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::affc60f14e638fb6890cc11efda7ef50
https://elib.dlr.de/105923/
https://elib.dlr.de/105923/
Publikováno v:
2016 IEEE AUTOTESTCON
Semiconductor products manufactured with latest and emerging processes are increasingly prone to wear out and aging. While the fault occurrence rate in such systems increases, the fault tolerance techniques are becoming even more expensive and one ca