Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Artjom Jasnetski"'
Publikováno v:
MIXDES
2017 MIXDES-24th International Conference "Mixed Design of Integrated Circuits and Systems
"2017 MIXDES-24th International Conference ""Mixed Design of Integrated Circuits and Systems"
"""2017 MIXDES-24th International Conference """"Mixed Design of Integrated Circuits and Systems"""
2017 MIXDES-24th International Conference "Mixed Design of Integrated Circuits and Systems
"2017 MIXDES-24th International Conference ""Mixed Design of Integrated Circuits and Systems"
"""2017 MIXDES-24th International Conference """"Mixed Design of Integrated Circuits and Systems"""
Software-based self-testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents a tool for automated Software-Based Self-Test program generation. The tool is based on the previously published methodology of us
Publikováno v:
2017 6th Mediterranean Conference on Embedded Computing (MECO)
MECO
MECO
A new high-level fault model and test generation method for software-based self-test in microprocessors (MP) is proposed and investigated. The model is derived directly from the instruction set of the given MP. A deterministic high-level method and a
Publikováno v:
2016 17th Latin-American Test Symposium (LATS)
LATS
LATS
Software-Based Self-Testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents an approach for automatic SBST program generation, based on the methodology of using High-Level Decision Diagrams (HLDD) for mode
Publikováno v:
EWME
Publikováno v:
LATW
Software-based self-testing (SBST) is a well known non-intrusive method for processor testing. Its applications have been intensively studied by the research community for the last decades. Generally, the inextinguishable attention to this method is
Publikováno v:
2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
DDECS
DDECS
The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation ar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b15093ff2ea463eabe0cb3fe4a700f49
Publikováno v:
Proceedings of the Estonian Academy of Sciences. 2014, Vol. 63 Issue 1, p48-61. 14p.
Publikováno v:
2016 IEEE 19th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS); 2016, p1-6, 6p
Publikováno v:
2016 17th Latin-American Test Symposium (LATS); 2016, p1-6, 6p
Publikováno v:
2015 IEEE 18th International Symposium on Design & Diagnostics of Electronic Circuits & Systems; 2015, p251-254, 4p