Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Arsen Hekimyan"'
Publikováno v:
2022 International Conference on Electrical, Computer and Energy Technologies (ICECET).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e048e659408eef54240f962ee808b57
https://doi.org/10.1109/icecet55527.2022.9872899
https://doi.org/10.1109/icecet55527.2022.9872899
Publikováno v:
EWDTS
Differential clock cross point correction method is presented in this paper. The proposed method provides differential clock with minimum crossing error over PVT, which is needed to improve noise immunity of Pipeline ADC. As Pipeline ADC work with di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4df5e716c5d08bd362384c37b1373351
https://doi.org/10.1109/ewdts.2016.7807647
https://doi.org/10.1109/ewdts.2016.7807647
Publikováno v:
2016 IEEE 36th International Conference on Electronics and Nanotechnology (ELNANO).
Capacitor mismatch correction method for Pipeline ADC is presented in this paper. The proposed architecture allows getting identical capacitors over PVT, which is needed to increase noise immunity and accuracy of ADC. Noise immunity of ADC is importa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92af1cb386b0f3815ffe8fd8d411d4d4
https://doi.org/10.1109/elnano.2016.7493076
https://doi.org/10.1109/elnano.2016.7493076
Publikováno v:
2015 Internet Technologies and Applications (ITA).
Analog-to-digital converters (ADCs) are devices which accept entrance analog signals and generate digital signals corresponding to them, suitable for processing by microprocessors and other digital devices. Requirements to ADCs constantly become toug
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d8fa85fb77156037bc67eafcee0de3eb
https://doi.org/10.1109/itecha.2015.7317415
https://doi.org/10.1109/itecha.2015.7317415
Autor:
Vazgen Melikyan, Aram Shishmanyan, Arsen Hekimyan, Tigran Khazhakyan, Arthur Sahakyan, Davit Trdatyan
Publikováno v:
EWDTS
A low power method of clock signal duty cycle adjustment is presented in this paper. The proposed architecture produces a synchronous signal in the output of system with 50±1% duty cycle over PVT, which is needed to avoid data error and setup/hold t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74c68780cc92805baafd0a9430d2e27f
https://doi.org/10.1109/ewdts.2015.7493157
https://doi.org/10.1109/ewdts.2015.7493157