Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Arnaud Poittevin"'
Autor:
Sara Mannaa, Arnaud Poittevin, Cedric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Ian O'Connor, Chhandak Mukherjee, Yifan Wang, Houssem Rezgui, Marina Deng, Cristell Maneux, Jonas Muller, Sylvain Pelloquin, Konstantinos Moustakas, Guilhem Larrieu
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 9, Iss 2, Pp 116-123 (2023)
This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphy
Externí odkaz:
https://doaj.org/article/880ac103a0f9440c8b6edc36da7ba0ce
Autor:
A. Bosio, Arnaud Poittevin, Thomas Mikolajick, S. Le Beux, Chhandak Mukherjee, Jens Trommer, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Zlatan Stanojevic, Oskar Baumgartner
Publikováno v:
EuroSOI-ULIS
EuroSOI-ULIS, Sep 2021, Caen, France
EuroSOI-ULIS, Sep 2021, Caen, France. ⟨10.1109/EuroSOI-ULIS53016.2021.9560180⟩
EuroSOI-ULIS, Sep 2021, Caen, France
EuroSOI-ULIS, Sep 2021, Caen, France. ⟨10.1109/EuroSOI-ULIS53016.2021.9560180⟩
To sustain transistor scaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) are a promising alternative. This work analyses the energy-delay-product (EDP) for a junction-less 3D ve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::530690b543af171c1e37f6997bc1e7a5
https://hal.archives-ouvertes.fr/hal-03407210/file/EUROSOI21_EDP_VF.pdf
https://hal.archives-ouvertes.fr/hal-03407210/file/EUROSOI21_EDP_VF.pdf
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2021, 183, pp.108125. ⟨10.1016/j.sse.2021.108125⟩
Solid-State Electronics, 2021, 183, pp.108125. ⟨10.1016/j.sse.2021.108125⟩
Solid-State Electronics, Elsevier, 2021, 183, pp.108125. ⟨10.1016/j.sse.2021.108125⟩
Solid-State Electronics, 2021, 183, pp.108125. ⟨10.1016/j.sse.2021.108125⟩
International audience; To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. To overcome the roadblocks of logic cell de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9df493ba17c4f490f6cb20e6470851da
https://hal.laas.fr/hal-03371661
https://hal.laas.fr/hal-03371661
Autor:
Alberto Bosio, Cedric Marchand, Arnaud Poittevin, Ian O'Connor, Mayeul Cantan, Marcello Traiola, Petr Fiser
Publikováno v:
2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna (virtual), Austria. pp.93-98, ⟨10.1109/DDECS52668.2021.9417062⟩
DDECS
2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna (virtual), Austria. pp.93-98, ⟨10.1109/DDECS52668.2021.9417062⟩
DDECS
In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior is turned into a design implementation in terms of logic gates. Historically, logic synthesis was tightly related to the physical imp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fddc660b86bd4de636c459cfba29a5ad
https://hal.archives-ouvertes.fr/hal-03266914
https://hal.archives-ouvertes.fr/hal-03266914