Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Arkadiy Morgenshtein"'
Autor:
Arkadiy Morgenshtein
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 2, Iss 1, Pp 69-78 (2012)
In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change o
Externí odkaz:
https://doaj.org/article/d8d41fffb6f940f6b3431c9e1e05bba5
Autor:
Jae Cheol Son, Jin Sung Park, Wookyeong Jeong, Arkadiy Morgenshtein, Wisam Kadry, Amir Nahir, Vitali Sokhin, Dimtry Krestyashyn, Sung-Boem Park
Publikováno v:
IEEE Design & Test. 34:65-76
Hardware-accelerated simulation platforms can significantly reduce the validation time. This article presents an off-platform test generation method and it compares and contrasts it against the on-platform alternative for two state-of-the-art multico
Publikováno v:
Integration. 47:62-70
Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The proposed methodology is applied to a 40nm Carry Look Ahead Adder (CLA). The CLA is implemented mainly using GDI full-swing F1 and F2 gates, which are the counterparts of standard
Autor:
Ronny Morad, Valeria Bertacco, Vitali Sokhin, Doowon Lee, Arkadiy Morgenshtein, Avi Ziv, Tom Kolan
Publikováno v:
DAC
Post-silicon validation has become essential in catching hard-to-detect, rarely-occurring bugs that have slipped through pre-silicon verification. Post-silicon validation flows, however, are challenged by limited signal observability, which impacts t
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:689-696
The unified logical effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic gates and resistive wires is presented. The method provides conditions for timing optimization while overcoming the limitations of standard l
Autor:
Wisam Kadry, Dimtry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae Cheol Son
Publikováno v:
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015.
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14:1276-1281
Logic gates as repeaters (LGRs)-a methodology for delay optimization of CMOS logic circuits with resistance-capacitance (RC) interconnects is described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentatio
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12:847-856
Novel gate-diffusion input (GDI) circuits are applied to asynchronous design. A variety of GDI implementations are compared with typical CMOS asynchronous circuits. Dynamic GDI state holding elements are 2/spl times/ smaller than CMOS C-elements, 30%
Publikováno v:
Sensors and Actuators B: Chemical. 98:18-27
The paper presents a novel readout configuration for ISFET sensors based on Wheatstone-Bridge connection. This design technique allows on-chip integration, temperature compensation and measurements from ISFET/REFET pairs. The circuit is capable of op
Publikováno v:
Sensors and Actuators B: Chemical. 97:122-131
CIMP (complementary ISFET/MOSFET pair)—a novel technique for implementation of readout interface in CMOS ISFET-based microsystems is described. This design technique allows body effect elimination, temperature compensation and design simplicity, wh