Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Aritoshi Sugimoto"'
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 20:549-555
A metrological definition and a target value for linewidth roughness (LWR) in a gate pattern of MOSFETs are proposed. The effects of sampling interval gate-LWR measurements by critical-dimension scanning electron microscopy on measurement accuracy we
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 17:104-110
A new test structure for the detection and localization of short and open defects in large-scale integrated intralayer wiring processes is proposed. In the structure, an open-monitoring element in the first metal layer meanders around lines of short-
Publikováno v:
Hyomen Kagaku. 20:27-32
Two-dimensional dopant profiles of LSI device cross-sections are extracted below 100nm scale from SCM (Scanning Capacitance Microscopy) technique. Sample cross-sections are prepared with a glass polishing technique, followed by a final polishing step
Publikováno v:
SPIE Proceedings.
Metrological definition and the target value of linewidth roughness (LWR) in gate pattern of MOSFETS are discussed. The effects of sampling interval of gate-LWR measurements using critical dimension scanning electron microscopy (CD-SEM) on the measur
Publikováno v:
Process and Materials Characterization and Diagnostics in IC Manufacturing.
An electron beam inspection is strongly required for HARI to detect contact and via defects that an optical inspection cannot detect. Conventionally, an e-beam inspection system is used as an analytical tool for checking the process margin. Due to it
Autor:
Aritoshi Sugimoto, K. Okuyama, H. Iwata, T. Kumazawa, S. Kamohara, Yuichi Hamamura, K. Nemoto
Publikováno v:
DFT
We propose a general method for repair yield estimation based on critical area analysis using a commercial Monte-Carlo simulator. We classify failures into several types according to the repair rules and use iterative critical area analysis for each
Publikováno v:
International Conference on Microelectronic Test Structures, 2003..
A new test structure for the detection and localization of short and open defects in LSI intra-layer wiring processes is proposed. In the structure, an open-monitoring element (OME) in the first metal layer meanders around lines of short-monitoring e
Killer defects control on patterned wafers for the sub quarter micron interconnect formation process
Publikováno v:
IWSM. 1998 3rd International Workshop on Statistical Metrology (Cat. No.98EX113).
Statistical yield modeling has become very practical and effective for defect control since CMP was first applied to the multilevel metallization process in order to achieve surface planarity. This paper presents a study of the defect size to be cont
Publikováno v:
1997 2nd International Workshop on Statistical Metrology.
This paper presents a method for discrimination of clustered defects. The histogram of the number of defects per die is approximated to several major distributions. As a result, we found that Poisson distribution is almost equivalent to real data. Th
Publikováno v:
SPIE Proceedings.
A high-throughput high-sensitivity defect-detection technique has been developed for manufacturing 0.15-0.25- micrometers LSI devices. It incorporates a high-resolution detection systems using multi-channel detectors and a high- resolution imaging sy