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pro vyhledávání: '"Arigala Joseph Jagarlamudi Manikanta"'
Autor:
Soniya Nuthalapati, Ch. Jyothirmayi, Galla. Saikiran, Chaitanya Prathikonda, Arigala Joseph Jagarlamudi Manikanta
This project visualizes the different designs of Full Adder (FADDR) circuits. These FADDR circuits are designed mainly to reduce the power and delay factors. If these two factors are minimized then automatically the power delay product (PDP) gets min
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______2659::d5a65226ef91364ec1b15bcc2b311184
https://zenodo.org/record/8094681
https://zenodo.org/record/8094681
