Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Ardie Venes"'
Autor:
Tianwei Li, Kowen Lai, Chi-Ming Hsiao, Xi Chen, Young Shin, Randall Perlow, Hanson Hung-Sen Huang, Ardie Venes, Ada Hing T. Hung, Vijayaramalingam Periasamy, Cynthia Dang, William Ngai, Chun-Ying Chen, Giuseppe Cusmai, Jerry Lin, Bryan Juo-Jung Hung, Loke Kun Tan, Pete Cangiane, Ning-Yi Wang, Gregory Unruh, Xicheng Jiang, Hong Liu, Ramon Gomez, Binning Chen, Yau-Cheng Yang, Maco Sha-Ting Lin, Tao Wang, Aravind Kumar Padyana, James Y. C. Chang, Massimo Brandolini, Ming-Hung Hsieh, Lakshminarasimhan Krishnan, Yen Ding, Deepak Lakshminarasimhan, Acer Wei-Te Chou, Jiangfeng Wu, Jianlong Chen, Yen-Jen Ko, Jackie Koon Lun Wong, Pin-En Su, Wei-Ta Shih, Chun-Sheng Huang, Vincent Cheng-Hsun Yang, Larry Wassermann, Bo Shen, Lin He, Ayaskant Shrivastava
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:845-859
A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital conve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12dabf14050ca7d254789f3785d92b46
https://doi.org/10.1109/jssc.2015.2511164
https://doi.org/10.1109/jssc.2015.2511164
Autor:
Mo Maggie Zhang, Young Shin, Hung Sen Huang, Yen-Jen Ko, Massimo Brandolini, Wei-Ta Shih, Giuseppe Cusmai, Chun-Sheng Huang, Chun-Ying Chen, Jiangfeng Wu, Yuan Yao, Bryan Juo-Jung Hung, Acer Wei-Te Chou, Rong Wu, Ayaskant Shrivastava, Yen Ding, Greg Unruh, Ming-Hung Hsieh, Ardie Venes, Tao Wang, Karthik Raviprakash, Hemasundar Mohan Geddada, Dominique Yi-Chun Chen, Tianwei Li
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:2922-2934
This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5cddea9b5d1b6c2ba10de1073415f58
https://doi.org/10.1109/jssc.2015.2464684
https://doi.org/10.1109/jssc.2015.2464684
Autor:
Koon Lun Jackie Wong, Tae-Youn Kim, Hans Eberhart, Sunny Raj Dommaraju, Chi-Hung Lin, Greg Unruh, Donald Edward Major, Ardie Venes, Guangxi Ray Xie
Publikováno v:
ISSCC
Advanced communication systems require DACs with high linearity over a wide bandwidth while consuming low power and small area [1]-[6]. In this work, a 16b 6GS/s Nyquist current-steering DAC in 16nm CMOS is presented. Utilizing bounded INL calibratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6ab275e704c0a3d78d178642bcdf00c
https://doi.org/10.1109/isscc.2018.8310333
https://doi.org/10.1109/isscc.2018.8310333
Autor:
Tai-Hong Chih, Guowen Wei, Ning-Yi Wang, Kuo-Ken Huang, Sunny Raj Dommaraju, Weinan Gao, Runhua Sun, James Y. C. Chang, Jiang Cao, Bo Shen, Vijay Periasamy, Jianhong Xiao, D.S.-H. Chang, Xiaojing Xu, Ardie Venes, Takayuki Hayashi, Xi Chen, Lakshminarasimhan Krishnan, Dongsoo Koh, Greg Unruh
Publikováno v:
VLSI Circuits
A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac606e1b8b65e114dcdb82ff6ca477c0
https://doi.org/10.1109/vlsic.2016.7573502
https://doi.org/10.1109/vlsic.2016.7573502
Autor:
Acer Wei-Te Chou, Young Shin, Hung-Sen Huang, Tao Wang, Juo-Jung Hung, Po Tang Yang, Chun-Ying Chen, Massimo Brandolini, Cheng-Hsun Yang, Tianwei Li, Sha-Ting Lin, Ardie Venes, Dongsoo Koh, Jiangfeng Wu, Gregory Unruh, Mo M. Zhang, Rong Wu, Qingqi Dou, Giuseppe Cusmai, Sunny Raj Dommaraju, H. Mohan Geddada, Xi Chen, Wei-Ting Lin
Publikováno v:
ISSCC
In recent years, we have seen the emergence of multi-GS/s medium-to-high-resolution ADCs. Presently, SAR ADCs dominate low-speed applications and time-interleaved SARs are becoming increasingly popular for high-speed ADCs [1,2]. However the SAR archi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::446e93d9536101ebfbfb08c00f6a9e9e
https://doi.org/10.1109/isscc.2016.7418109
https://doi.org/10.1109/isscc.2016.7418109
Autor:
Sivakumar Ganesan, Xuefeng Yu, Jose Fabian Silva-Rivas, Shankar Thirunakkarasu, Kannan Deenadayalan, Frank Singor, Jie Fang, Nand Jha, Chaoming Zhang, Bharath Kumar Thandri, Ardie Venes
Publikováno v:
MWSCAS
A highly linear, 3rd order, active-RC low-pass elliptic filter with Variable Gain Amplifier (VGA) is presented. The new derivative-free biquad topology for an elliptic filter could be easily extended to a higher order filter using a cascade of biquad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4069a78fe5722aa4e276fc8e0341e67e
https://doi.org/10.1109/mwscas.2015.7282083
https://doi.org/10.1109/mwscas.2015.7282083
Autor:
Karthik Raviprakash, Hemasundar Mohan Geddada, Chun-Sheng Huang, Ardie Venes, Yen Ding, Chun-Ying Chen, Wei-Te Chou, Yen-Jen Ko, Ayaskant Shrivastava, Ming-Hung Hsieh, Rong Wu, Giuseppe Cusmai, Yi-Chun Chen, Tao Wang, Tianwei Li, Mo M. Zhang, Greg Unruh, Juo-Jung Hung, Hung Sen Huang, Massimo Brandolini, Young Shin, Jiangfeng Wu, Wei-Ta Shin
Publikováno v:
ISSCC
The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (∼5GS/s), mid-resolution (∼10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2071599f52751d9a3f2b4970305fd35
https://doi.org/10.1109/isscc.2015.7063129
https://doi.org/10.1109/isscc.2015.7063129
Publikováno v:
IEEE Journal of Solid-State Circuits, 34(12), 1753-1764. Institute of Electrical and Electronics Engineers
This paper presents a sixth-order continuous-time bandpass sigma-delta modulator (SDM) for analog-to-digital conversion of intermediate-frequency signals. An important aspect in the design of this SDM is the stability analysis using the describing fu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3db8e02941f9bccc2eae2b82983723d9
https://research.tue.nl/en/publications/62e56aaf-cff5-4b63-a13d-e89936150e37
https://research.tue.nl/en/publications/62e56aaf-cff5-4b63-a13d-e89936150e37