Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Arch Zaliznyak"'
Publikováno v:
ISQED
Physical verification of components in 2.5D and 3D integrated chips is challenging because existing tool flows have evolved from monolithic silicon design. These components are typically designed on separate technology nodes nearly independent of eac
Autor:
Ramanand Venkata, Seungmyon Park, Ning Xue, Lana May Chan, John Lam, Rakesh H. Patel, Chong Lee, M. Lai, Malik Kabani, Arch Zaliznyak, Vinson Chan, Tam Nguyen, S. Shen, Michael Menghui Zheng, Divya Vijayaraghavan, Huy Ngo, Binh Ton
Publikováno v:
CICC
Several strategies that were employed for developing next-generation embedded Hard IP are reviewed. Mixed signal Hard IP developed for a multi-protocol serial interface physical layer at 0.622Gbps to 3.125Gbps was redeployed for 0.622Gbps to 6.375Gbp
Autor:
Tin H. Lai, Arch Zaliznyak, Chong Lee, Kazi Asaduzzaman, John Lam, Shoujun Wang, Binh Ton, Wilson Wong, Victor Maruri, Simardeep Maangat, Henry Y. Lui, Huy Ngo, Tim Tri Hoang, Ramanand Venkata, Tam Nguyen, Mei Luo, Tung Hoang Tran, Toan Nguyen, Malik Kabani, Rakesh H. Patel, Vinson Chan, S. Shumurayev
Publikováno v:
CICC
The SoPC (system on a programmable chip) aspects of the Stratix GX/spl trade/ FPGA with 3.125 Gbps SERDES are described. The FPGA was fabricated on a 0.13 /spl mu/m, 9-layer metal process. The 16 high-speed serial transceiver channels with clock data
Conference
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