Zobrazeno 1 - 3
of 3
pro vyhledávání: '"April Gurba"'
Autor:
Rajesh Khamankar, Joe G. Tran, P.E. Nicollian, Anand T. Krishnan, Melissa M. Hewson, S. Aur, Mark Somervell, James Walter Blatchford, Tad Grider, Lindsey H. Hall, Brian K. Kirkpatrick, D. Farber, Srinivasan Chakravarthi, Benjamen Michael Rathsack, H. Bu, Brian Hornung, Juanita Deloach, Brian A. Smith, Jiong-Ping Lu, C. Kaneshige, April Gurba, C. Bowen, C. Machala, Donald S. Miles, Husam N. Alshareef, M. J. Bevan, P.R. Chidambaram, Vladimir A. Ukraintsev, Ajith Varghese, Hiroaki Niimi
Publikováno v:
Scopus-Elsevier
In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel str
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7bea0f7129ea088a7c5308d5ef089297
https://doi.org/10.1109/vlsit.2004.1345456
https://doi.org/10.1109/vlsit.2004.1345456
Autor:
D. Mercer, Melissa M. Hewson, Tad Grider, Clinton L. Montgomery, R. Kuan, L. Tsung, Donald S. Miles, J. Ruan, J. Zhao, April Gurba, C.T. Lin, Jiong-Ping Lu, Y. Xu
Publikováno v:
Digest. International Electron Devices Meeting.
A novel nickel self-aligned silicide (SALICIDE) process technology has been developed for CMOS devices with physical gate length of sub-40 nm. The excess silicidation problem due to edge effect is effectively solved by using a low-temperature, in-sit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6eae55f6a0c71ccde57a5b0c8a7d2356
https://doi.org/10.1109/iedm.2002.1175855
https://doi.org/10.1109/iedm.2002.1175855
Autor:
Husam N. Alshareef, Juanita Deloach, M. J. Bevan, C. Bowen, M. Goodwin, P.R. Chidambaram, James Walter Blatchford, Srinivasan Chakravarthi, Tad Grider, Brian K. Kirkpatrick, Rajesh Khamankar, April Gurba, Ajith Varghese, Hiroaki Niimi, Donald S. Miles, Brian A. Smith, Xin Zhang, C. Machala, Jiong-Ping Lu, Lance S. Robertson, G.V. Thakar, Benjamen Michael Rathsack, Brian Hornung, P.E. Nicollian
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
A 90 nm logic technology is presented featuring an aggressively scaled 37 nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f9fff4d3ed93400052c81221e1ec69b
https://doi.org/10.1109/vlsit.2003.1221098
https://doi.org/10.1109/vlsit.2003.1221098