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pro vyhledávání: '"Aparajithan Nathamuni-Venkatesan"'
Autor:
Aparajithan Nathamuni-Venkatesan, Ram-Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
Reverse engineering of FPGA based designs from the flattened LUT level netlist to high level RTL helps in verification of the design or in understanding legacy designs. We focus on flattened netlists for FPGA devices from Xilinx 7 series and Zynq 700
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6fd4d559bd5910b2536ecfaf03d1f193
