Zobrazeno 1 - 10
of 70
pro vyhledávání: '"Anujan Varma"'
Publikováno v:
IEEE/ACM Transactions on Networking. 14:532-542
Many recent router architectures decouple the routing engine from the forwarding engine, allowing packet forwarding to continue even when the routing process is not active. This opens up the possibility of using the forwarding capability of a router
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7da8920e428c29e6dba9ec2fc7c74e98
https://doi.org/10.1109/tnet.2006.876152
https://doi.org/10.1109/tnet.2006.876152
Autor:
Anujan Varma, Dimitrios Stiliadis
Publikováno v:
IEEE/ACM Transactions on Networking. 6:175-185
Although weighted fair queueing (WFQ) has been regarded as an ideal scheduling algorithm in terms of its combined delay bound and proportional fairness properties, its asymptotic time complexity increases linearly with the number of sessions serviced
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c56af2983a697717a6ee858251716743
https://doi.org/10.1109/90.664266
https://doi.org/10.1109/90.664266
Autor:
Dimitrios Stiliadis, Anujan Varma
Publikováno v:
IEEE/ACM Transactions on Networking. 6:164-174
Generalized processor sharing (GPS) has been considered as an ideal scheduling discipline based on its end-to-end delay bounds and fairness properties. Until recently, emulation of GPS in a packet server has been regarded as the ideal means of design
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4b42a36ab97472f3f77dffdda208631a
https://doi.org/10.1109/90.664265
https://doi.org/10.1109/90.664265
Publikováno v:
IEEE/ACM Transactions on Networking. 6:729-743
We study the performance of bidirectional TCP/IP connections over a network that uses rate-based flow and congestion control. An example of such a network is an asynchronous transfer mode (ATM) network using the available bit rate (ABR) service. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22b6426bb7a43fdf383ffc6a30214cb1
https://doi.org/10.1109/90.748085
https://doi.org/10.1109/90.748085
Autor:
Anujan Varma, Q. Jacobson
Publikováno v:
IEEE Transactions on Computers. 47:228-235
In a disk array with a nonvolatile write cache, destages from the cache to the disk are performed in the background asynchronously while read requests from the host system are serviced in the foreground. We study a number of algorithms for scheduling
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91d9cb28cb71b5587b94232052ba40d0
https://doi.org/10.1109/12.663770
https://doi.org/10.1109/12.663770
Autor:
Anujan Varma, Lampros Kalampoukas
Publikováno v:
IEEE/ACM Transactions on Networking. 6:599-610
This paper provides an analysis of the source policy in the rate-based congestion control scheme developed by the Asynchronous Transfer Mode (ATM) Forum for available bit rate service and derives approximate analytical closed-form expressions to desc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92942809503dea0aac11a8afa28c1fbf
https://doi.org/10.1109/90.731195
https://doi.org/10.1109/90.731195
Autor:
Anujan Varma, Dimitrios Stiliadis
Publikováno v:
HICSS (1)
Although direct-mapped caches suffer from higher miss ratios as compared to set-associative caches, they are attractive for today's high-speed pipelined processors that require very low access times. Victim caching was proposed by Jouppi (1990) as an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ea20b84a18240ad2282e7b7df9929f02
https://doi.org/10.1109/12.589235
https://doi.org/10.1109/12.589235
Autor:
Dimitrios Stiliadis, Anujan Varma
Publikováno v:
IEEE Communications Magazine. 35:54-68
Providing quality-of-service guarantees in both cell- and packet-based networks requires the use of a scheduling algorithm in the switches and network interfaces. These algorithms need to be implemented in hardware in a high-speed switch. The authors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4940b7008050ec4dc2be9e7ab9985106
https://doi.org/10.1109/35.642834
https://doi.org/10.1109/35.642834
Autor:
Anujan Varma, Dimitrios Stiliadis
Publikováno v:
ACM Transactions on Modeling and Computer Simulation. 7:131-156
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3377dea583cb031a1a2d6f756fdc4506
https://doi.org/10.1145/244804.244809
https://doi.org/10.1145/244804.244809
Autor:
Quinn Jacobson, Anujan Varma
Publikováno v:
ISCA
In a disk array with a nonvolatile write cache, destages from the cache to the disk are performed in the background asynchronously while read requests from the host system are serviced in the foreground. In this paper, we study a number of algorithms
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::263f4c1853c00578ed9cdbe62980ecad
https://doi.org/10.1145/225830.224042
https://doi.org/10.1145/225830.224042