Zobrazeno 1 - 10
of 35
pro vyhledávání: '"Anuj Pathania"'
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 10, Iss 4, p 31 (2020)
Multiple multi-threaded tasks constitute a modern many-core application. An accompanying generic Directed Acyclic Graph (DAG) represents the execution precedence relationship between the tasks. The application comes with a hard deadline and high peak
Externí odkaz:
https://doaj.org/article/e08d57e082974f9e9e637f94a8ccf624
Publikováno v:
DATE
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE 2021): virtual conference 1-5 February 2021, 1192-1197
STARTPAGE=1192;ENDPAGE=1197;TITLE=2021 Design, Automation & Test in Europe Conference & Exhibition (DATE 2021)
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE 2021): virtual conference 1-5 February 2021, 1192-1197
STARTPAGE=1192;ENDPAGE=1197;TITLE=2021 Design, Automation & Test in Europe Conference & Exhibition (DATE 2021)
Coarse-Grained Reconfigurable Array (CGRA) has emerged as a promising hardware accelerator due to the excellent balance among reconfigurability, performance, and energy efficiency. The CGRA performance strongly depends on a high-quality compiler to m
Autor:
Anuj Pathania, Jorg Henkel, Sami Salamin, Hussam Amrouch, Arka Maity, Martin Rapp, Tulika Mitra
Publikováno v:
IEEE Transactions on Computers. 70:1484-1497
Multi-/many-core, homogeneous or heterogeneous architectures, using the existing CMOS technology are inevitably approaching the limit of attainable power efficiency due to the fundamental limits in scaling. Negative Capacitance Field-Effect Transisto
Publikováno v:
2022 25th Euromicro Conference on Digital System Design (DSD).
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:2254-2267
IoT Edge intelligence requires Convolutional Neural Network (CNN) inference to take place in the edge devices itself. ARM big.LITTLE architecture is at the heart of prevalent commercial edge devices. It comprises of single-ISA heterogeneous cores gro
Publikováno v:
IEEE Design & Test. 37:50-57
The ever-increasing demand from mobile Machine Learning (ML) applications calls for evermore powerful on-chip computing resources. Mobile devices are empowered with heterogeneous multi-processor Systems-on-Chips (SoCs) to process ML workloads such as
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(2), 306-319. Institute of Electrical and Electronics Engineers Inc.
Streaming applications, consisting of several communicating kernels, are ubiquitous in the embedded computing systems. The synchronous data flow (SDF) is commonly used to capture the complex communication patterns among the kernels. The general-purpo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::698baf18c175a5cc3fc320ad9e54e84b
https://dare.uva.nl/personal/pure/en/publications/chordmap-automated-mapping-of-streaming-applications-onto-cgra(84451cef-07cd-4491-92c9-8eb6e03e3443).html
https://dare.uva.nl/personal/pure/en/publications/chordmap-automated-mapping-of-streaming-applications-onto-cgra(84451cef-07cd-4491-92c9-8eb6e03e3443).html
Publikováno v:
IEEE Transactions on Computers. 69:1-22
Publikováno v:
IEEE Transactions on Computers. 69:1-13
Two factors primarily affect the performance of multi-threaded tasks on many-core processors with logically-shared and physically-distributed Last-Level Cache (LLC): the LLC latencies of threads running on different cores and the per-core power budge
Publikováno v:
ACM Transactions on Embedded Computing Systems. 18:1-26
A Coarse-Grained Reconfigurable Array (CGRA) is a promising high-performance low-power accelerator for compute-intensive loop kernels. While the mapping of the computations on the CGRA is a well-studied problem, bringing the data into the array at a