Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Antonio R. Pelella"'
Autor:
Howard H. Smith, Antonio R. Pelella, Patrick J. Meaney, Pradip Patel, D. Malone, G. Gerwig, S. Carey, William V. Huott, James D. Warnock, David L. Rude, Thomas Strach, Frank Malgioglio, Huajun Wen, Daniel Rodko, Yuen Chan, Paul A. Bunce, Jose L. Neves, Yiu-Hing Chan, John Davis
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:151-163
This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 cont
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e540a64872963d1dea4d5479786ea8c0
https://doi.org/10.1109/jssc.2011.2169308
https://doi.org/10.1109/jssc.2011.2169308
Autor:
Bargav Balakrishnan, Antonio R. Pelella, Pradip Patel, Richard E. Serton, Daniel Rodko, Yuen H. Chan
Publikováno v:
ISSCC
With the push to ever higher core frequencies, more logic functions are making their way onto critical path SRAMs in the L1 cache look up structure. Described in this paper is a 14 bit dynamic hit logic scheme with an embedded 8K bit SRAM in IBM's 45
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ba9eb75cc92b1bf56ad1d375b1897a2
https://doi.org/10.1109/isscc.2011.5746224
https://doi.org/10.1109/isscc.2011.5746224
Publikováno v:
2008 IEEE International SOI Conference.
Super fast Monte-Carlo techniques are applied to allow deeper insight to the yield of SOI domino circuit design techniques for SRAMs. For the first time, Read-before-Write in dual supply domino bit-select design is analyzed in the presence of floatin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c25511df90da2822d4022b0b47d23ac
https://doi.org/10.1109/soi.2008.4656285
https://doi.org/10.1109/soi.2008.4656285
Autor:
K. Lo, Paul A. Bunce, Pradip Patel, William V. Huott, Y.H. Chan, Antonio R. Pelella, Thomas J. Knips, E. Fluhr, Donald W. Plass, Rajiv V. Joshi, A. Chen, John Davis
Publikováno v:
ISSCC
A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per P0WER6 core is presented. The array utilizes a 0.75mum2 butted-junction split-word line 6T cell in 65nm SOI. The design features dual power suppli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1fd545fced750b60b84f615a9dce85f
https://doi.org/10.1109/isscc.2006.1696322
https://doi.org/10.1109/isscc.2006.1696322
Publikováno v:
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
An 8Kb domino read SRAM with hit logic and parity checker, fabricated in a 65nm SOI CMOS technology (Leobandung, 2005), is described. A key feature is the elimination of the traditional sense amplifier to reduce timing and design complexity. The focu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a7d4adbe12b108d2e1bce8b583bb60ea
https://doi.org/10.1109/esscir.2005.1541634
https://doi.org/10.1109/esscir.2005.1541634
Autor:
S. Kowalczyk, Pradip Patel, Y.H. Chan, Antonio R. Pelella, J. Rawlins, U. Bakhru, P.T. Wu, William V. Huott, Pong-Fei Lu
Publikováno v:
1996 Symposium on VLSI Circuits. Digest of Technical Papers.
High speed level-1 cache applications demand fast single cycle access times and short cycles. Novel circuits that deliver fast access times and self-resetting CMOS (SRCMOS) techniques that deliver fast cycle times are described. Two key elements for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6efc6cfe339c94dcc0bab5abb083a774
https://doi.org/10.1109/vlsic.1996.507741
https://doi.org/10.1109/vlsic.1996.507741
Autor:
Steve Wilson, Dennis G. Manzer, Yuen Chan, Moyra K. McManus, Antonio R. Pelella, Daniel R. Knebel, William V. Huott, Steven E. Steen, Pia Naoko Sanda, Stas Polonsky
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
Picosecond imaging circuit analysis (PICA) is recently demonstrated to be a practical measurement technique of internal timing of ICs. This paper describes application of PICA to analysis of individual MOSFET switching times in the L1 cache write con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e316ef0e09d72259594cdbbbd0d9decf
https://doi.org/10.1109/isscc.2000.839758
https://doi.org/10.1109/isscc.2000.839758
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