Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Anton Tsertov"'
Publikováno v:
Proc. IEEE European Test Symposium 2019 (in press)
ETS
ETS
The increasing number of embedded instruments used to perform test, monitoring, calibration and debug within a semiconductor device has called for a brand new standard—the IEEE 1687. Such a standard resorts to a reconfigurable scan network to provi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::92ce52f0aafe07466b4e84b6346cc9b3
This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016. The 11 papers included
Publikováno v:
MIXDES
2017 MIXDES-24th International Conference "Mixed Design of Integrated Circuits and Systems
"2017 MIXDES-24th International Conference ""Mixed Design of Integrated Circuits and Systems"
"""2017 MIXDES-24th International Conference """"Mixed Design of Integrated Circuits and Systems"""
2017 MIXDES-24th International Conference "Mixed Design of Integrated Circuits and Systems
"2017 MIXDES-24th International Conference ""Mixed Design of Integrated Circuits and Systems"
"""2017 MIXDES-24th International Conference """"Mixed Design of Integrated Circuits and Systems"""
Software-based self-testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents a tool for automated Software-Based Self-Test program generation. The tool is based on the previously published methodology of us
Publikováno v:
2017 6th Mediterranean Conference on Embedded Computing (MECO)
MECO
MECO
A new high-level fault model and test generation method for software-based self-test in microprocessors (MP) is proposed and investigated. The model is derived directly from the instruction set of the given MP. A deterministic high-level method and a
Publikováno v:
IFIP Advances in Information and Communication Technology ISBN: 9783319671031
VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability
VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cf5cc3cc71fd2a268b7dd77315b5f24
https://doi.org/10.1007/978-3-319-67104-8
https://doi.org/10.1007/978-3-319-67104-8
Publikováno v:
DDECS
When facing in-field board test, the functional approach plays an important role. Often, it corresponds to forcing the processor to execute a test program (which could be an application one), observing the produced results (e.g., by looking at the re
Publikováno v:
2016 17th Latin-American Test Symposium (LATS)
LATS
LATS
Software-Based Self-Testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents an approach for automatic SBST program generation, based on the methodology of using High-Level Decision Diagrams (HLDD) for mode
Publikováno v:
EWME
Publikováno v:
Asian Test Symposium
While system level test was a topic of extremely high interest during the last decades, the cost of the test program development was continuously growing. The restricted capabilities of Boundary Scan (BS) with respect of such modern challenges as dyn
Publikováno v:
DSD
Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interes