Zobrazeno 1 - 10
of 69
pro vyhledávání: '"Antoine Cros"'
Publikováno v:
Solid-State Electronics
Solid-State Electronics, 2016, 123, pp.84-88. ⟨10.1016/j.sse.2016.06.004⟩
Solid-State Electronics, Elsevier, 2016, 123, pp.84-88. ⟨10.1016/j.sse.2016.06.004⟩
Solid-State Electronics, 2016, 123, pp.84-88. ⟨10.1016/j.sse.2016.06.004⟩
Solid-State Electronics, Elsevier, 2016, 123, pp.84-88. ⟨10.1016/j.sse.2016.06.004⟩
International audience; A new Y-function based MOSFET parameter extraction method is proposed. This method relies on explicit expressions of inversion charge and drain current versus Yc(=Qi√Cgc)-function and Y(=Id/√gm)-function, respectively, app
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d51ee41a652fb594772a3bfabaa83e94
https://doi.org/10.1016/j.sse.2016.06.004
https://doi.org/10.1016/j.sse.2016.06.004
Publikováno v:
2018 International Integrated Reliability Workshop (IIRW).
non uniform field TTDB stress have been performed on 28nm FDSOI MOSfet devices. After analysis of thermal effects under increasing drain voltage, as well as potential TDDB-HCI interactions, a complete TTDB model, taking into account non uniform field
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef5a935a1ae0412acfa55595c2d1f5af
https://doi.org/10.1109/iirw.2018.8727096
https://doi.org/10.1109/iirw.2018.8727096
Publikováno v:
IRPS
In this paper, we analyze the impact of the self-heating observed on Back End of Line (BEoL) structures and NMOS transistors in 28nm FDSOI technology. Metal characterization is required to calculate the thermal resistance (Rth). A given model relates
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a377d6a1add50a90ef83ec6dbaea76e8
https://doi.org/10.1109/irps.2018.8353673
https://doi.org/10.1109/irps.2018.8353673
Autor:
Mireille Mouis, Ming Shi, Antoine Cros, Gerard Ghibaudo, Emmanuel Josse, Gyu Tae Kim, Minju Shin
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2015, 108, pp.30-35. ⟨10.1016/j.sse.2014.12.013⟩
Solid-State Electronics, 2015, 108, pp.30-35. ⟨10.1016/j.sse.2014.12.013⟩
Solid-State Electronics, Elsevier, 2015, 108, pp.30-35. ⟨10.1016/j.sse.2014.12.013⟩
Solid-State Electronics, 2015, 108, pp.30-35. ⟨10.1016/j.sse.2014.12.013⟩
International audience; In this work, we demonstrate the powerful methodology of electronic transport characterization in highly scaled (down to 14 nm-node) FDSOI CMOS devices using cryogenic operation under interface coupling measurement condition.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eed4ffc243ca21903e450b1095e4688e
https://doi.org/10.1016/j.sse.2014.12.013
https://doi.org/10.1016/j.sse.2014.12.013
Publikováno v:
2017 ICMTS Proceedings
2017 International Conference of Microelectronic Test Structures (ICMTS)
2017 International Conference of Microelectronic Test Structures (ICMTS), Mar 2017, Grenoble, France. pp.68-72, ⟨10.1109/ICMTS.2017.7954269⟩
2017 International Conference of Microelectronic Test Structures (ICMTS)
2017 International Conference of Microelectronic Test Structures (ICMTS), Mar 2017, Grenoble, France. pp.68-72, ⟨10.1109/ICMTS.2017.7954269⟩
session 4: Device modelling; International audience; In this work, an upgraded version of the so called New Y function MOSFET parameter extraction methodology is proposed, taking the impact of access resistance into account. This new approach emphasi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1c54d75372d89c11b8969dd6f4d228eb
https://doi.org/10.1109/icmts.2017.7954269
https://doi.org/10.1109/icmts.2017.7954269
Autor:
Denis Rideau, Antoine Cros, Gerard Ghibaudo, Julien Rosa, A. Soussou, Sebastien Haendler, C. Diouf
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2013, 86, pp.45-50. ⟨10.1016/j.sse.2013.04.024⟩
Solid-State Electronics, Elsevier, 2013, 86, pp.45-50. ⟨10.1016/j.sse.2013.04.024⟩
In this paper, we investigate the impact of silicon–germanium channel on PMOSFETs with TiN metal and HfSiON dielectrics gate stack. Performance increase with Ge incorporation in the channel is higher than theoretically expected. Threshold voltage i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e4370caa7daa94b0734b1e334ad41638
https://doi.org/10.1016/j.sse.2013.04.024
https://doi.org/10.1016/j.sse.2013.04.024
Autor:
Gerard Ghibaudo, G. Bidal, Flore Kergomard, A. Bajolet, Antoine Cros, Cheikh Diouf, Julien Rosa, R.A. Bianchi, Lama Rahhal
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2013, 85, pp.15-22. ⟨10.1016/j.sse.2013.03.001⟩
Solid-State Electronics, Elsevier, 2013, 85, pp.15-22. ⟨10.1016/j.sse.2013.03.001⟩
In this work, P-MOS transistors of advanced bulk technology integrating high K/metal gate and SiGe channel are considered. An exhaustive study of threshold voltage (Vt), current gain factor (β), and drain-current (Id) mismatches with different Ge pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9dda9e947662c00b1f46be90d3048d1a
https://doi.org/10.1016/j.sse.2013.03.001
https://doi.org/10.1016/j.sse.2013.03.001
Autor:
Louis Hutin, J. Mazurier, D. Barge, L. Pasini, Olivier Weber, Frédéric Mazen, F. Piegas Luce, Claire Fenouillet-Beranger, M. Vinet, Antoine Cros, E. Ghegin, B. Mathieu, S. Chhun, J. Borrel, Frederic Boeuf, Quentin Rafhay, Anthony Payet, Michel Haond, Perrine Batude, M. Casse, Fuccio Cristiano, Benoit Sklenard, Zineb Saghi, Joris Lacord, D. Blachier, J.P. Barnes, Gerard Ghibaudo, Francois Andrieu, V. Mazzocchi, N. Rambal, J. Micout, Vincent Delaye, V. Lapras, Laurent Brunet, R. Daubriac, Pascal Besson
Publikováno v:
Proceedings of the 2016 IEEE Symposium on VLSI Technology
2016 IEEE Symposium on VLSI Technology
2016 IEEE Symposium on VLSI Technology, Jun 2016, Honolulu, United States. ⟨10.1109/VLSIT.2016.7573407⟩
2016 IEEE Symposium on VLSI Technology
2016 IEEE Symposium on VLSI Technology, Jun 2016, Honolulu, United States. ⟨10.1109/VLSIT.2016.7573407⟩
International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::733572509907569cf7c31dbc0cecdb89
https://hal.laas.fr/hal-01730659
https://hal.laas.fr/hal-01730659
Publikováno v:
2016 ICMTS Proceedings
2016 International Conference on Microelectronic Test Structures (ICMTS)
2016 International Conference on Microelectronic Test Structures (ICMTS), Mar 2016, Yokohama, Japan. pp.70-75, ⟨10.1109/ICMTS.2016.7476177⟩
2016 International Conference on Microelectronic Test Structures (ICMTS)
2016 International Conference on Microelectronic Test Structures (ICMTS), Mar 2016, Yokohama, Japan. pp.70-75, ⟨10.1109/ICMTS.2016.7476177⟩
session 4: Parameter extraction; International audience; In this work, an improved methodology of access resistance extraction is proposed and applied on dedicated Kelvin test structures from a FD-SOI 14 nm technology. The use of this new approach an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7b98c2361f885d276c492749914ef0b1
https://hal.archives-ouvertes.fr/hal-01959130
https://hal.archives-ouvertes.fr/hal-01959130
Publikováno v:
2016 IEEE International Reliability Physics Symposium (IRPS)
One of major CMOS reliability concern for advanced nodes is the Bias Temperature Instability mechanism. In addition to the native local process dispersion, BTI induced dispersion is becoming a field of intensive research. Important works focus on the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::455ef810514eb3775787e38b42836d5e